Vdd is 5V. The bias current of this circuit is 100μA. The load capacitance (CL) is 5pF. Va (the voltage at the gate of the PMOS devices) is 4.2V. The PMOS current mirror is 1:1. Assume everything is in the saturation region. Include proper units for full credit and show your work. Unless otherwise specified and if appropriate, give an equation and a number answer. For the circuit shown above, answer the following questions: (i) What is the width of device 2? (Ignore channel length modulation (λ) ). (10pts) (ii) What is the width of device 1? (Again, ignore channel length modulation (λ)) (8pts) (iii) What is the small signal gain in terms of gmx (transconductance) and gox (output conductance) where x is 1 or 2, the device number? The output transconductance of PMOS 3 can be neglected. Be sure to draw the small signal model for full credit. (8pts) (iv) (Extra Credit) What is the value of the small signal gain? (4pts)
Consider the circuit to the right. Vdd = 10 V, R2 = 20 kΩ, R4 = 2 kΩ, kn = 10 mA/V2 and Vtn = 1.5 V. Find values for R1 and R2 such that ID = 300 μA ± 1%. What is VDS in this case?
(2pts) Using the constant voltage drop (CVD) diode model, what is the value of Vo for the circuit shown in Figure 2? Assume standard silicon diodes with VD = 0.7 V. Figure 2 Vdd = 3.3 V R = 10 kΩ V1 = 1 V V2 = 2 V Vo = 2.7 V Vo = 1 V Vo = 2 V Vo = 1.7 V
Problem 3: BJTs (28pts) R1 = 2 kΩ, R2 = 20 kΩ VA is large, so you can neglect go. IB = 15 μA Include proper units for full credit and show your work. Unless otherwise specified and if appropriate, give an equation and a number answer. For the circuit shown above, answer the following questions: (v) (Extra Credit) What is the numeric value of the small signal gain? (2pts) (vi) (Extra Credit) What is the value of the input resistance at the base of the transistor? (2pts)
Problem 5: CMOS Power Dissipation and Propagation Delay (12pts) An IC inverter fabricated in a 0.18 μm CMOS process is found to have a load capacitance of 110 fF. The inverter is operated from a 1.8 V power supply. The IC chip has 1 million inverters operating at a switching frequency is 3 GHz. For the delay calculations, you can approximate the NMOS and PMOS transistors with 1 kΩ and 2 kΩ resistances, respectively. Show your equations and number answer. (i) How much energy is required to charge and discharge the load capacitance? (4pts) (ii) What is the dynamic power dissipation of the entire IC? (4pts) (iii) What is the average current drawn from the power supply? (4pts) (iv) (Extra Credit) For each inverter, what is the propagation delay for the output voltage going high to low? (2pts)
Problem 1: What Logic Function (show Truth Table and Boolean Equation for Y = f(A, B)) does the following circuit perform? Hint: make a Truth Table showing every possible combination of inputs. HIGH voltage to Bubble FETS turns them OFF), LOW Voltage ON. Converse for non-Bubble FETs. For some combinations output Y will connected ('pulled up') to Vdd, for others connected to ('pulled Hint: make a Truth Table showing every possible combination of inputs. HIGH voltage to Bubble FETS turns them OFF), LOW Voltage ON. Converse for non-Bubble FETs. For some combinations output Y will connected ('pulled up') to Vdd, for others connected to ('pulled down') to ground (LOW). down') to ground (LOW).
Consider the following MOS Amplifier where R1 = R2 = 13 kΩ, RD = 21 kΩ, IS = 0.23 mA, and RL = 100 k Ω. The MOSFET parameters are: knW/L = 5 mA/V, VT = 0.6 V, and λ = 0.013 V−1. Find the voltage gain vout /vin
D *7.121 The MOSFET in the circuit of Fig. P7.121 has Vt = 0.8 V, kn = 5 mA/V2, and VA = 40 V. (a) Find the values of RS, RD, and RG so that ID = 0.4 mA, the largest possible value for RD is used while a maximum signal swing at the drain of ±0.8 V is possible, and the input resistance at the gate is 10 MΩ. Neglect the Early effect. (b) Find the values of gm and ro at the bias point. (c) If terminal Z is grounded, terminal X is connected to a signal source having a resistance of 1 MΩ, and terminal Y is connected to a load resistance of 10 kΩ, find the voltage gain from signal source to load. (d) If terminal Y is grounded, find the voltage gain from X to Z with Z open-circuited. What is the output resistance of the source follower? Figure P7.121 (e) If terminal X is grounded and terminal Z is connected to a current source delivering a signal current of 50 μA and having a resistance of 100 kΩ, find the voltage signal that can be measured at Y. For simplicity, neglect the effect of ro.
Use the circuit diagram and sensor characteristic plot below to answer the following questions. Assume that VDD is 8 V. Enter numerical answers in the units specified, but do not type in the unit names or their abbreviations. Determine the resistance, in ohms, of sensor RLDR when it is exposed to a light intensity of 600 lux. Answer: R1 = Ω. Use your answer for the resistance of the sensor to find the required value of R2, in ohms, if a light intensity of 600 lux only just turns the LED, D1, on. You can assume that D1 is a green LED with a forward voltage drop of 2.2 V . Answer: R2 = Ω. Finally, calculate the minimum size of R3 if the maximum allowable LED current is 20 m A . Answer: R3 = Ω.
The parameters of the MOSFET in the circuit shown below are VTN = −1 V, Kn = 1.7 mA/V2, and λ = 0.02 V−1. a) Determine the values of RS and RD such that IDQ = 0.1 mA and a maximum symmetrical 1V peak sinusoidal signal occurs at the output. b) Find the small-signal transistor parameters. c) Determine the small-signal voltage gain Av = vo/vs.
For the following problem, neglect body effect, Cgd and ro, but consider Cgs and use long-channel equations in transistors. Assume L = 0.7 μm for both transistors. The other circuit component values are the following: Rb = 4 kΩ, Rd = 50 Ω, Lg = 10 nH, Ls = 0.5 nH, RS = 50 Ω. The frequency of operation is 2.4 GHz. Ci may be considered as a short circuit at the frequency of operation. Rb is high enough that can be considered as an open circuit for small signal. (a) Symbolically, calculate the input impedance Zi. (b) Calculate the required overdrive voltage in M2 to make the real part of Zi equal to 50 Ω. (c) Calculate W2 to make Zi = 50 Ω. (d) Calculate ID and W1 to make Iref = ID/10. (e) Calculate the DC component at v0. (f) Numerically calculate the small-signal gain, av = vo/vi. (g) Calculate vo if vs = 1 mV peak. (h) Symbolically, calculate the noise figure of this amplifier. (i) Calculate F in dB. CMOS process data: VDD = 1.8 V. For NMOS, Vthn = 0.4V, μn = 400 cm2/Vs, Cox = 9 fF/μm2 and γn = 1. The parameters for PMOS transistors are k′ = μpCox = 90 μA/V2, Vthp = −0.4V and γp = 0.8.