Multistage Amplifier In this last question, you are going to design a 2-stage amplifier. The first stage is a common-source amplifier and the second is a source follower, as shown in the figure below: Some parameters you may use are: VDD = 5 V, μnCox = 0.2 mA/V2, μpCox = 0.1 mA/V2, λn = 0.06, λp = 0.03, γ = 0, VTHN = 0.7 V, VTHP = −0.6 V; allow RL = 2 KΩ. Note: CS is large enough so that it will act as a short circuit for frequencies of interest. The circuit should satisfy the following specs: Total power consumption = 6.5 mW (use this spec to find total current drawn from VDD) The ratio of power consumed by the biasing branch: the amplifier: the follower stage should be 1:2:10 CS stage should provide a gain equal to −40 V/V Source follower stage should have a gain of 0.6 V/V Vomax = 3.8 V Find the W/L of all transistors and value of RD. Make reasonable simplifications.
The basic diff BJT below provides a differential input resistance (Rid = 2rπ) of 50 kΩ. Design the amplifier (choose the value of RC) to provide a differential voltage gain of 38 dB. Let β = 100. 20 KOhm 3.25 KOhm 1.50 KOhm 25 KOhm
Problem 7.3 (20 points) Consider an ideal op-amp network depicted in Figure P7.3. (a) What are the terminal voltages (v−, v+) and currents (i−, i+) of the inverting and noninverting terminals, respectively. (b) Express the output voltage V0 in terms of the resistors and the input voltages Vs1, Vs2. Does it depend on the load resistor RF? Then evaluate V0. Figure P7.3 Vs1 = 6 V, Vs2 = 2 V, Rs = 1 kΩ, RF = 4 kΩ, RL = 2 kΩ
Problem 7.4 (20 points) Consider an ideal op-amp network shown in Figure P7.4. (a) Find the voltage ratio V2/V1. (b) Find the voltage ratio V0/V2. (c) Determine the overall voltage gain GV = V0/V1. Figure P7.4 RA = 20 kΩ, RB = 80 kΩ, R1 = 1 kΩ, R2 = 24 kΩ
The trip point of a CMOS inverter is 0.6 V. The NMOS and PMOS devices have identical Cox, L and the magnitudes of their threshold voltages are both 0.2 V. You are also given that μn = 2.μp. Find the width of the NMOS transistor if the width of the PMOS transistor is 200nm. Assume that VDD = 1 V.
2-Consider the Circuit below a-)What is the logic function implemented by the CMOS transistor network? b-)Size the NMOS and PMOS devices so that the output resistance is the same as that of an inverter with an NMOS W/L = 4 and PMOS W/L = 8. C-) If P(A = 1) = 0.5, P(B = 1) = 0.2, P(C = 1) = 0.3 and P(D = 1) = 1, determine the power dissipation in the logic gate. Assume VDD=2.5V, Cout = 30 fF and fclk = 250 MHz. (To find the switching activity you must calculate the Pγ(0−1) = Pγ=1×Pγ=0 = Pγ=0×(1−Pγ=1)