5-2. A logic gate noise margin parameters are: VIH = 1.6 V, VIL = 0.3 V, VOH = 1.7 V, and VOL = 0.2 V. (a) Calculate NMH. (b) Calculate NML. (c) The input voltage is down to 1.7 V and a negative 50 mV noise spike appears. What happens to the circuit fidelity? (d) The input voltage is down to 1.7 V and a negative 150 mV noise spike appears. What happens to the circuit fidelity?
Given the circuit shown in the following figure, and based on the 180 nm TSMC Technology, assume that the supply voltage (VDD) is 1.8 V, and the length of each transistor (n-type MOSFET) is fixed at L = 180 nm. Make reasonable assumptions for the widths of these transistors. Analyze this circuit by calculation and identify the regions of operation of the two MOSFETs and the drain-source current (IDs) of the MOSFETs, assuming that the transistors are ON. The threshold voltage of the MOSFET is given by Vth = 0.5 V, and μnCox = 70 μA/V2. Also given: VB = 0.7 V, and R = 1 KΩ.
A common-source amplifiers utilizes a MOSFET operated at VOV = 0.1 V. The amplifier feeds a load resistance RL = 30 kΩ. The designer selects RD = 20 kΩ. If it is required to realize an overall voltage gain Gv of −12 V/V, what bias current ID is needed? Express your answer in mA. Type in the value of ID without the unit (mA).
Consider the above circuit, if the input voltages are zero what are the two currents, output voltages, the virtual ground voltage, and VOV for both transistors? Then assume that VG1 = VG2 = Vin, what is the highest value of Vin such that the transistors remain in saturation? What is the lowest value of Vin such that the current source will still function properly (Assume the current supply transistor operates at the VOV as input transistors)? If VG2 is fixed to 0V, what is minimum VG1 s.t. the entire bias current flows through Q1 and conversely the maximum VG1 s.t. the entire bias current flows through Q2. What are the corresponding output and virtual ground voltages? The transistors have a 0.4 V threshold and 16 mA/V2 kn.
This differential amplifier has an active current-mirror load. Find Ro and Ad, if the bias current is 0.3 mA, all transistors have a length of 0.4 micron, the differential-pair transistors have W/L of 20 and the process node has μnCOX = 500 μA/V2 and |VA′| = 6 V/μm. What value of a load resistor will halve the gain?