You are given a folded-cascode op amp shown to the left. VDD = VSS = 1 V. Vtn = −Vtp = 0.4 V. For all transistors, |VA| = 6 V. Power dissipated in the circuit (with no input signal applied) is 0.6 mW. Q1 and Q2 operate at a current that is four times that at which Q3 and Q4 is operating. All transistors operate at |VOV| = 0.2V. Show the current drawn from each of the two power supplies is 2IB. Find IB and I that result in the circuit operating at its specified power dissipation. Find the DC current at which each of Q1 to Q11 operate Find the input common-mode range Find the allowable range of Vo. Find the overall transconductance Gm Find the output resistance R0
The following circuit is designed to work with ID1' = ID2' = ID3' = 1 mA and all transistors are in the saturation region. For all these transistors VA = 50 V, and Kn = Kp = 1 mA/V2. Calculate the small signal gain, Vo/Vi. Hint: You replace Q3 with its equivalent resistance. Then use replace Q2 with its output resistance to calculate the gain. Keep in mind Vg2 and Vg3 are replaced by grounds in the small signal model. (20)
Cascode Stage. Design a Cascode amplifier shown in figure below to achieve a gain of 1600. Assume VDD = 1 V, Vth = 0.3 V, λn = 0.2 V−1, γ = 0, μnCox = 100 μA/V2, I1 = 1 mA, gmro ≫ 1. a) Find bias point (VGS−Vth of transistors) to achieve the target gain such that we achieve maximum swing at Vout. b) Find W/L for each transistor. c) Calculate optimal Vb and VIN DC bias to maximize output swing. What is this maximum/minimum voltage levels at the output? What is the maximum swing? d) Notice you must generate a specific Vb externally to maximize the swing. If a lazy designer decides to connect Vb to VDD instead, what would be the swing in this case? e) To realize the current source load, we will use a PMOS active load. For PMOS, use the same parameters with λp = 0.2 V−1, μpCox = 50 μA/V2. Assume the bias current will remain at 1mA, find the new gain value. What would be the W/L for PMOS if we want to have a VOD(VGS−Vth) of 0.1V for this device. f) Repeat part (e) for a PMOS load with 2L gate length. g) It seems like making the PMOS load very large (large W) is beneficial to reduce VOD and consequently improving the voltage swing. What do you think is the drawback?
In the circuit below, the MOSFET has K = 2 mA/V2 and VT = 1 V. The BJT has β = 100. (a) Find the minimum value of VIN for which Q1 will operate in forward active and M1 will operate in saturation. (b) Set VIN = 3 V. Find VOUT and IDS. Draw the small-signal model. (c) Find the small-signal voltage gain A = vout/vin. (d) Find the small-signal input resistance, rin. (e) Find the small-signal output resistance, rout .
A) Which configuration is this circuit 1-CS, 2-CG, 3- CD (Source Follower) B) Draw small signal equivalent circuit including body effect. C) Find Voltage gain for gmb = χgm where χ = 0.1 to 0.2, (a)
Consider the differential amplifier shown below, where the value of bias current is I = 200 μA. The resistor is RC = 9.7 kΩ and VCC = 3 V. What is the maximum common-mode input voltage for which operation keeps both transistors in the active mode? Please give your answer in two decimal places.
FETS can be used to either pull an output high or to pull it low, but NFETs are generally better in digital applications for pulling outputs low and PFETs for pulling outputs high. Consider an NFET with characteristics: kn′ = 115 μA/V2, VT0 = 0.43 V, λ = 0.06 V−1, VDSAT = 0.6 V, W/L = 2, and a supply voltage of Vdd = 2.0 V, Vin = 2.0V. a. Say the NFET is used to pull a capacitor high. i. How high can the NFET pull the output voltage and still be turned "on"? ii. Consider the output voltage in question (i) as Vmax. When the output voltage is within 0.1 V of its maximum(ie, Vout = Vmax−0.1 ), what state is the NFET in (saturation, cut-off, linear)? iii. What is the current, approximately, through the NFET when Vout = Vmax −0.1?
In Fig. 4, VDD = 2.5 V, R2 = 20 kΩ, R3 = 30 kΩ, (W/L)1 = (2/0.1), and CC is very large. Determine R1 such that the amplifier gain is maximized with the constraint that the output (Vout) has at least 200mVpp of swing. (20)
22. In Fig. 6, VDD = 3 V, VB = 3 V, (W/L)1 = (W/L)3 = (10μm/0.1μm), (W/L)2 = (20μm/0.1μm). (a) For Vin = 1.8V, calculate Vout and ID2. (10) (b) Calculate the small-signal gain of this amplifier @Vin =1.8V. Figure 6 μnCox = 100 μA/V2, μpCox = 40 μA/V2, Vthn = |Vthp| = 0.5 V, λn = λp = 0
In Fig. 5, VDD = 10 V, (W/L)1 = (1/0.1), (W/L)2 = (10/0.1), I1 = 100 μA, I2 = 150 μA. C1 is very large. Assume that all the transistors are in saturation. μnCox = 100 μA/V2, μpCox = 40 μA/V2, Vthn = |Vthp| = 0.5 V, λn = λp = 0 (a) For Vin = 2 V, determine VX. (b) Determine the small-signal gain of the amplifier. Figure 5
In Fig. 4, VDD = 2.5 V, (W/L)1 = (W/L)2 = (100/0.1), VB = 1 V, R1 = 10 Ω. C1 is very large. μnCox = 100 μA/V2, μpCox = 40 μA/V2, Vthn = |Vthp | = 0.5 V, λn = λp = 0 (a) Determine the small-signal gain Vout/Vin. (10) (b) Determine the minimum input bias voltage. (10) Figure 4
24. In Fig. 7, VDD = 3 V, (W/L)1 = (20μm/0.2μm), (W/L)2 = (W/L)3 = (W/L)4 = (10μm/0.2μm), R1 = R2 = R3 = 100 kΩ. C1 and C2 are very large, and VB1 = 2 V, VB2 = 1 V. λn = λp = 0.01/V (a) Express the small signal gain of this amplifier using the small signal parameters of MOSFETs (gm, ro) and the resistance of resistors (R1, R2, R3). (10) (b) Ignoring the channel length modulation, determine Vin so that Vx = 2.5 V. (10) (c) Determine the small signal gain of the amplifier at the value of Vin obtained in (b).(10) Figure 7 μnCox = 100 μA/V2, μpCox = 40 μA/V2, Vthn = |Vthp | = 0.5 V, λn = λp = 0
In Fig. 5, VDD = 2.5 V, VB1 = 1 V, RG = 100 kΩ, RD = 10 kΩ, R1 = 10 kΩ, (W/L)1 = (W/L)2 = (W/L)3 = (W/L)4 = (1/0.1). CC1∼CC3 are very large. (a) Determine the VB2 such that the output (Vout) swing is maximized while all MOSFETs operate in the saturation region. (b) For a dc input of Vin = 1 V, determine Vx, Vz and Vout. Fig. 5 (c) When Vin(t) = 1[V] + 10[mV]sin(ωt) is applied, determine Vout(t). (10)
In Fig. 6, VDD = 5 V, VB = 2.5 V, IB = 500 μA, RD = 5 kΩ, (W/L)1 = (1/0.1). CC is very large. (a) Determine the Vp and Vout at bias. (b) Determine the gain of the amplifier. (5) Figure 6 μnCox = 100 μA/V2, μpCox = 40 μA/V2, Vthn = |Vthp| = 0.5 V, λn = λp = 0
(40 points) MOSFET Amplifiers. a. (10 points) For the MOSFET amplifier circuit shown below, draw and label a small signal equivalent circuit. In your small signal equivalent circuit, include coupling capacitors CG1, C12, and CS2 and the Cgd and Cgs of each transistor. b. (10 points) For the ampifier in part a, the current sources have a Norton resistance of 8K Ohms. The load is 5K Ohms. Find the midband voltage gain Av. For transistor M1 ro = 12KOhms ID = 2mA VGS = 0.8V For transistor M2 ro = 10KOhms ID = 1.8mA VGS = 0.7V c. For the small signal equivalent circuit shown below, find the poles of the circuit. You may use Miller's approximation. d. For a step function for the input voltage in the switching MOSFET circuit shown below, estimate the time it takes for vgs to rise to 4.8 Volts. The transistors are a CMOS pair with Cgs = 1.0 nF for the NMOS and Cgs = 0.5 nF for the PMOS. Cgd is too small to be significant for this calculation.
Q1. Consider the logic circuit shown in Fig. P7.10, with VTO (enhancement) = 1 V, VTO (depletion) = −3 V, and γ = 0. (a) Determine the logic function F. (b) Calculate WL/LL such that VOL does not exceed 0.4 V. (c) Qualitatively, would WL/LL increase or decrease if the same conditions in (b) are to be achieved but γ = 0.4 V1/2? Fig. P7.10
(40 points) MOSFET Large Signal Analysis. For an NMOS device in the circuit shown below, the following data applies: μnCox = 200 μA/V2 W = 5.0 μm L = 180 nm VTH = 0.40 V λ = 0.0 Neatness and accuracy of plots is a big part of the grade for this problem. a. (12 points) For VDS ranging from 0.0 Volts to 2.5 Volts, plot ID vs VDS for VGS = 0.60 Volts. Label the point where the triode region and the saturation region intersect on this trace. Write and draw big on your plots. b. (10 points) On the your ID vs VDS plot, draw the ID vs. VDS line for the Thevenin circuit formed by VDD, RD, and the drain-source part of the MOSFET. Label the intersections at each axis. c. (8 points) Find and label the intersection of the two plots for parts a and b with the following format: (VGS=…,VDS=…,ID=…). d. (10 points) For vGS(t) = 0.60 + 0.05sin(2π1000t) Volts, determine and plot iD(t). Label the maximum and minimum points for iD(t) with the format: (VGS=…,VDS=…,ID=…).
Q2. For the gate shown in Fig. P7.5, Pull-up transistor ratio is 5/5 pull-down transistor ratios are 100/5 VT0 = 1.0 V γ = 0.4 V1/2 |2ϕF| = 0.6 V (a) Identify the worst case input combination(s) for VOL. (b) Calculate the worst case value of VOL. (Assume that all pull-down transistors have the same body bias and initially, that VOL ≈ 5% VDD∗ ) Fig. P7.5
For the circuit shown below, the NMOS transistor has Vtn = 0.5 V, kn = 1 mA/V2 and λn = 0, and the PMOS transistor has Vtp = −0.5 V, kp = 12.5 mA/V2, and |λp| = 0. Analyze the circuit to determine the currents in all branches and the voltages at all nodes. Note that the NMOS transistor (Q1) and its surrounding resistors are the same as the circuit you analyzed in Question 5. You may use the results found in Question 4 here.
7. In the circuit above, the MOSFET and BJT have the following parameters,[5∗6=30] K = 4 mA/V2, VT = 0.9 v, β = 100, VBE(active) = 0.7v, VBE( sat) = 0.8 v a. Find out the gate voltage of the MOSFET. b. Calculate V1. c. Find out the expression for VGS, VDS & Vov d. Find the operating mode of the MOSFET using the expressions from. [Hint: You don't need any assumption] e. Calculate IDS and VDS using the given parameters. f. Assume that the BJT is in the saturation mode. Now, calculate IB, IC, IE. You must validate the given assumption. Figure-3
A CMOS amplifier is shown in Figure 3. PMOS transistors M1 and M2 have μpCox = 60 μA/V2, Vtp = −0.4 V, |1/λp| = 100 V, W = 240 μm and L = 1.6 μm. The NMOS transistor M0 has parameters μnCox = 90 μA/V2, Vtn = 0.4 V, 1/λn = 100 V, W = 160 μm and L = 1.6 μm. VDD = 5 V and Rref = 100 kΩ. Figure 3 (i) Calculate the current flowing in the reference resistor Rref . (ii) Sketch Vo as a function of Vi, indicating the regions of operation of the transistors. (iii) Calculate the small-signal voltage gain vo/vi when M0 and M1 are biased in their saturated regions of operation. (iv) If the DC and small-signal components of Vi and Vo are denoted ViQ, VoQ and vi, vo respectively, what value of voltage ViQ is required to give ID0Q = 45 μA? To simplify the calculation, you may neglect channel length modulation effects. (v) Calculate the numerical value of the small-signal voltage gain vo/vi when ViQ has the value derived in part (iv).
(20 points) MOSFET Biasing. a. (10 points) For the circuit shown on the left below, bias the MOSFET in the saturation region at the point VDS = 1.25 V, ID = 1.0 mA. Let VDD = 2.5 V. This means specify a value for RD, R1, and R2. Keep the power loss in the combined R1 and R2 below 12.5 μW. b. (10 points) Because resistors are known to occupy too much area on chip, we want to bias this MOSFET with a transistor circuit instead as shown below. The two transistors M1 and M2 are identical, having also identical values of W/L, ID and VDs to those given in part a, but M3 has a different W/L. Find the W/L ratio of M3.
In this amplifier circuit, the high and low DC voltage sources are: VDD = 5 V and VSS = −5 V respectively. Consider that all three external capacitors have high values. The PMOS transistor has a threshold voltage equal to Vt = −1 V and kp = kp′(W/L) = 0.4 mA/V2, and the NMOS transistor has a threshold voltage Vt = 1 V and a kn = kn′(W/L) = 2 mA/V2. It was shown in HW#7 that the DC drain voltage of the PMOS transistor is −0.2 V and the DC source of the NMOS transistor is −2 V. a) Perform the small signal analysis of this circuit and determine the voltage gain: AV = Vo/Vi b) Determine the input and output resistance of this amplifier Rin and Rout . c) Discuss what is the purpose of the part of the circuit between CC2 and CC3 which includes the NMOS transistor in this amplifier design. d) Determine the parameters of a simple voltage amplifier model (discussed in chapter 1) which will represent this amplifier. Note that the parameters of the simple voltage amplifier excludes any series resistance of the external source ( Vi ) (in this case it is zero anyway) and the load resistance (in this case RL = 2 kΩ ). e) Using the simple model from part (c) determine the voltage gain AV = Vo/Vi and see if it agrees with the answer of part (a). VDD
5. The voltage transfer characteristic (VTC) of a CMOS inverter is shown in Figure 5 . The threshold voltages for the NMOS and PMOS devices are +0.4V and -0.4 respectively. Assume the transistors are well-matched with identical μCox(W/L) values. 5.1. What is the value of Vdd? What is Vee? 5.2. Determine the states of the two FETs (cut-off, linear, or saturation) at points A, B, C, and D on the VTC. Write your answers in the table below. 5.3. Which point(s) on the VTC would produce the lowest static power consumption? 5.4. Place a large dot on the VTC at the point of largest dynamic power consumption.Figure 5 CMOS inverter w voltage transfer curve.
An RC series circuit consists of a 10. 0V battery, a 750 Ohm resistor, and a 200 μF capacitor. 0.15 s 750 microseconds 0.750 seconds 1.50 milliseconds
(DRAM operations) For a 1T-1C DRAM cell in a densely packed DRAM array, (a) During the write operation, to achieve a full VDD on the dynamic node X, three strategies have been proposed: (1) Extended write time; (2) WL boosting; (3) BL boosting. Which one(s) will be effective? (5 pts) (b) During the read operation, if we have Ccell = 5fF, CBL = 20fF and VDD = 1. 2V, what is the voltage perturbation on BL during the read operation? (5 pts)
AC Steady State & Transfer Functions (25 points)(a) Obtain the transfer function H(ω), and determine the zeroes and poles. (10 points) (b) Plot the Bode plot (of the transfer function gain) (15 points)H(ω) = Vout/Vin
For the two-stage n-MOSFET amplifier circuit shown below, assume that K′ = 1mA/V2 and VT = 1V for all MOSFETs. (a) Find the DC voltages VIN, VOUT1 and VOUT2 . (b) Draw the small-signal model for the circuit assuming a small signal source is applied at the node marked vIN. Find the small signal voltage gains: A1 = vout1/vin; A2 = vout2/vout1; ATotal = vout2/vin . (c) What is the small-signal input resistance, rin?
The schematic of the basic current mirror that utilizes MOSFETs is shown in Figure 1. Assume that the MOSFETs are identical and ignore the channel modulation effect for current transfer ratio calculations. Use Vtn = 2V, Kn = 150mA/V2, and VA = 50V. (Keep in mind that both Vtn and Kn can vary between transistors. A suggested range for Vtn is 1. 8 to 2. 2V and Kn can range from 120mA/V2 to 180mA/V2 ). Figure 1 - Basic MOSFET Current Mirror. Since the VGS voltages of the MOSFETs are the same, the drain current ID2 is equal to ID1. The source VDD2 ensures that Q2 is in saturation mode. Q2 "mirrors" Q1 and hence the circuit is called current mirror. Design the circuit of Figure 3 to obtain IREF = 80mA. Use VDD1 = 7V and VDD2 = 5V. 1. 1. 1 Calculate the value of VGS required for IREF = 80mA. 1. 1. 2 Calculate the value of R. 1. 1. 3 Determine the values of gm and the output resistance of the current mirror r0.
At the end of this assignment is a set of characteristic curves for an n-channel JFET. Print out the curves, and look at the one labeled "nJFET #1." The curves are label with the gate-source voltage (VGS) values. (a) Estimate the IDSS from the curve. (b) Estimate the gate-source threshold voltage VT. (c) Plot the load line on the graph when the nJFET is used in this circuit. (d) We want to set the quiescent point to be near the middle of the full possible output voltage range (about halfway between 0V and VDD = 15V). Mark the quiescent point with "Q" on the load line. (e) What is the transconductance near the quiescent point? (f) What should the DC voltage be set to in order to properly bias the transistor? (Assume that the DC voltage can be adjusted to any positive or negative value, and that the AC amplitude is zero for now). (g) The AC voltage now has an amplitude of 0. 5V (in other words, VG oscillates ±0. 5V around the VDC value). Use the graph to determine the maximum and minimum values for the drain current. (h) Based on the max and min drain currents, what are the max and min values for Vout ? And based on this peak-peak output swing, what is the AC gain of the circuit? (i) What is the AC gain of the circuit of you calculate it directly from the transconductance and the circuit components?