Given a 64M × 1 DRAM. Each memory cell needs to be refreshed every 50 ms and the refresh time is 40 ns. Determine (i) the number of rows and columns in the memory array configuration, (ii) the refresh period for each row, (iii) the number of refresh cycles which can be accommodated within one refresh period, and (iv) briefly discuss the reason of arranging the memory array in a square.
A DRAM cell uses a storage capacitor of 30 fF, VDD = 3.0 V and VT = 0.5 V for the NMOS access FET. If the bit line capacitance is 149 fF, the leakage current is 5 nA, and the memory is refreshed every 1 μsec, then what is the minimum voltage in millivolts that the sense amp must be able to detect as a valid one? Answer: The correct answer is: 391.1
a) The CMOS inverter of Figure Q4 is implemented in a 0.13−μm process for which μNCox = 500 μA/V2, μPCox = 125 μA/V2, VTN = −VTP = 0.4 V, and VDD = 1.2 V. The NMOS transistor has (W/L)N = 1.5. (i) What must (W/L)p be if QN and Qp are to have equal Ron resistances? (5 marks) (ii) Find the value of RoN. ( 5 marks) Figure Q4 b) Design a symmetric CMOS inverter to achieve a delay of 300 ps when driving a 250 fF load using a 3.3 V power supply. Assume the following parameters: Threshold voltages VTN = −VTP = 0.7 V, KN = 100 μA/V2, KP = 40 μA/V2. Transconductance parameter (N) KN′ = 100 μA/V2, Transconductance parameter (P) KP = 40 μAV2. (15 marks)
Question (1): For a CMOS Inverter in 0.25 μm technology, VDD = 3 V, given that: kn′ = 115 μA/V2, kP′ = 30 μA/V2, VDS satn = 0.63 V, VSD satp = 1 V, Vthn = 0.43 V, Vthp = −0.4 V, λn = 0.06 V−1, λp = −0.1 V−1, and (W/L)p = 1.5 pMOS transistor (L: 0.025 μm/λ, Average width: 4 λ, and Activity factor = 0.01 ) nMOS transistor (L: 0.025 μm/λ, Average width: 2 λ, and Activity factor = 0.02 ) C = 1 fF/μm (gate) +0.6 fF/μm (diffusion) For Symmetric VTC find: (a) The Switching Threshold VM, VDS, VGS, VSD, and VSG. (b) (WL)n. (c) VIL, VIH, NML, and NMH. (d) tpHL, tpLH, tp, and the maximum switching frequency (Assume total capacitance at the output node is 5 fF). (e) Calculate the propagation delay needed to deliver a signal to Cext = 1.5 pf. (f) Estimate the dynamic power consumption at 2.5 GHz ?
Part 1: Design of a CMOS Inverter Objective: Design a CMOS inverter so as to achieve a given performance specification. Figure 1. CMOS Inverter Consider a CMOS inverter such as the one shown in Figure 1. For the NMOS driver, use VT0 = 0.4 V, kn′ = 432 μA/V2, 2ϕF∣ = 0.88 V, γ = 0.2 V1 /2, λ = 0 V−1, Wn = 25 μm, and Ln = 0.1 μm. For the PMOS load, use VT0 = −0.4 V, kp′ = 108 μA/V2, |2ϕF| = 0.88 V, γ = 0.2 V1 /2, λ = 0 V−1, and Lp = 0.1 μm. ⇒ Design the inverter - i. e. , determine the value of Wp for the PMOS load - so as to make the noise margins equal: NML = NMH. In order to limit calculation complexity while still obtaining a reasonably accurate estimate, use the long-channel equations for NMOS and PMOS devices calculations. Round your calculated value of Wp to the nearest multiple of 0.05 μm. ⇒ Using your rounded value for Wp, calculate the expected value for the switching threshold, Vth. ⇒ Lastly, double the rounded value of Wp, then calculate the revised value of the switching threshold, Vth . Comment on the effect of decreasing the ratio KR = kdriver kload .
Part 2: Analysis of a CMOS Inverter's Dynamic Behavior Objective: Perform hand calculations of switching delays through a CMOS inverter. Consider a CMOS inverter such as the one shown in Figure 2. The delay times, trise and tsunv , will be determined by the current-driving capacities of the PMOS and NMOS transistors, respectively, as well as the magnitude of the load capacitance CL. Figure 2. CMOS Inverter The rise time trice for a CMOS inverter can be calculated as: tnse = CLΔV IDAvg , where IDP wg is the average of the PMOS currents at the 10% point of the low-to-high transition (Vout = Vtow ) and at the 90% point (Voor = Vsow ). Likewise, the fall time tfall for a CMOS inverter can be calculated as: tsanl = CLΔV IDavg , where ID timg is the average of the NMOS currents at the 90% of the high-to-low transition (Vout = VSop ) and at the 10% point (Vous = V10%). ⇒ Calculate the expected rise and fall times, trise and tfall . Use LCM equations with a load capacitance value of 25 pF. Use VT0 = 0.4 V, kn′ = 432 μA/V2, |2ϕϝ| = 0.88 V, γ = 0.2 V1 /2, λ = 0 V−1, WN = 2 μm, and LN = 100 nm for the NMOS device. Use Vpv = −0.4 V, kp′ = 108 μA/V2, |2ϕF| = 0.88 V, γ = 0.2 V1 /2, λ = 0 V−1, Wp = 8 μm, and Lp = 100 nm for the PMOS device.
In the following CMOS inverter k = 2.5 mA/V2, Vt = 1 V, VDD = 5 V. (a) Find V0 if Vl = 0 V (b) Find V0 if Vl = 5 V (c) Find the drain current ID when VI = 2.5 V (20 points)
In a CMOS inverter, power is consumed during the transitional switching of the PMOS and NMOS devices. Explain the source of the current glitch seen in the figure belowHow could this current glitch be reduced to save power? A particular IC chip can dissipate 10 W and contains 5 million CMOS inverters. Each inverter is being switched at frequency f a. Determine the average power that each inverter can dissipate without exceeding the total allowed power b. If the switching frequency is f = 5 MHz, what is the maximum capacitive load on each inverter if VDD = 3.3 V
For the CMOS inverter if the parameters are changed as follow: For NMOS: Vtn = 0.5 V and kn = 1.1 mA/V2 and (λ = 0) For PMOS: |Vtp| = 0.6 V and kp = 1.6 mA/V2 and (λ = 0) and VDD = 1.8 V. Find the new value for VM. VM, new = (V)
A CMOS inverter is to be designed to achieve a delay of 300 pF when driving a 250 fF load using a 2.5 V supply. Assume that the threshold voltages of the CMOS technology are VTN = −VTP = 0.7 V and KN′ = 100 μAN2 and KP′ = 40 μA/V2 Calculate (W/L)P
In an ideal CMOS inverter, there is static power dissipation. zero extremely low very low infinite Question 2 (20 points) In a symmetrical CMOS inverter, transconductance parameter for PMOS, Kp, is not equal to the transconductance parameter for NMOS, KN. True False
Question 2 Consider a CMOS inverter where device parameters PMOS and NMOS are not matched. The transistor device parameters are: kn = 0.5 (mA/V2), Vtn = 1.5 V, kp = 1(mAV2), Vtp = −1 V, CL = 1 pF, VDD Use λ = 0 in your analysis. (a) Find Vin when ∂Vo/∂Vin is infinite on the VTC curve. Vin =
The CMOS inverter of Fig 1. is implemented in a 0.13 μm process, determine (W/L)n and (W/L)p so that tPLH = tPHL = 50 ps when the effective load capacitor C = 20 fF. Fig. 1. The CMOS inverter with the effective load capacitor
CMOS inverter design Figure 2 shows the design of a CMOS inverter. WN = 420 nm and WP = 504 nm. CL = 20 fF, which is added in the test bench, not in the schematic. a. Plot out the voltage transfer characteristic (VTC), which is the curve of Vout vs. Vin , when Vin sweeps from 0 to VDD. b. Apply a ramp input to Vin , which is a 0 to VDD switching, with the transition time Tr = 30 ps (as shown in Figure 2). Plot out the waveform of Vout. Measure the 50% VDD delay (i. e. , time Figure 2. The schematics of a CMOS inverter difference from the 50% point of input to the 50% point of output) and the time for Vout to transit from 90%−10%VDD .
Assume we have a CMOS inverter with a voltage transfer curve given below. VDD = 1.5 V, Vtn = 0.2 V, Vtp = −0.2 V Which one is the valid ratio of βp/βn for this inverter? a) 5 b) 1 c) 0.2 At point Q, what are the most possible operating regions for nmos and pmos of this inverter? (Cut off Linear Saturation) nmos = pmos = Compute the noise margins NML and NMH. NML = v NMH = v
Unloaded CMOS Inverter. The CMOS inverter is constructed with nmos and pmos devices with parameters of: nmos:(W/L)n = 50.18, μnCox = 200 μA/V2, VTn = 0.4 volts, λn = 0.1 V−1 and pmos:(W/L)p = 100.18, μpCox = 100 μA/V2, VTp = −0.4 volts , λn = 0.15 V−1. The suypply voltage is VDD = 1.8 V. a) Find the gate bias voltage (Vg) which results in a zero output voltage. b) Find the gate bias voltage (Vg) which results in a zero output voltage if both transistors were sized the same.
a) For the CMOS inverter shown below, calculate and plot the dc quasi-static current that flows through the transistor as a function of 0 ≤ VIN ≤ VDD. Given: VDD = 5 V For n-MOSFET: μnCOX = 20 μA/V2 W/L = 2 and Vth, n = 1 V For p-MOSFET: μpCOX = 10 μA/V2 W/L = 4 and |Vth,p| = 1 V Where Vth,n and Vth,p are threshold voltages of n-and p-MOSFETs. L and W are channel length and gate width of the MOSFET. μ is the mobility of carriers in the channel region. COX is the gate gate oxide capacitance /area. MOSFET I-V Relations: ID = 0.5 μCOX(W/L){2(VGS−Vth)VDS−VDS2} (Linear region) ID = 0.5 μCox(W/L){(VGS−Vth)2} (Saturation region) Where VGS is the gate-to-source voltage and ID is the drain current. b) Compute dynamic power dissipation if now a square wave input with time period TP is applied to input. Given CL = 0.01 pF and TP = 100 ns.
Consider CMOS inverter with symmetric voltage transfer characteristic. Assume VDD = 2.5 V. Unloaded inverter demonstrates propagation delay of ∼100 ps; When 10 pF load capacitance is connected between output and ground (Figure) the measured propagation delay becomes equal to 100 ns. Estimate the propagation delay when load capacitance becomes equal to 100 pF. Estimate the maximum switching frequency for inverter loaded with 100 pF. Find the dynamic power dissipation for unloaded, loaded with 10 pF and loaded with 100 pF inverters operated at switching frequency found in question 2.
Question 1 A) Please find the following based on the VTC curve of an inverter shown in Figure 1: Figure 1: VTC curve of a CMOS inverter i. VOH, VOL, VIL, VIH, and VM ii. Noise margin iii. Based on the value of the VM, state the condition of this CMOS inverter of whether this is a "good PMOS, bad NMOS" or a "bad PMOS, good NMOS" inverter iv. You're required to redesign the above inverter to have a faster performance. Please indicate on how can this design is achieved with respect to the variation of VM
(CMOS inverter) (total: 40 pts) Considering the following CMOS inverter circuit with long-channel ideal n/p MOSFET and voltage transfer characteristics, (a) Derive the VIL and VIH equation and show that NML = NMH if βn = βp and Vth, n = |Vth,p| (8 pts) (Note: βn = μnCoxWn/Ln, βp = μpCoxWp/Lp and assume body-effect coefficient 'm' is 1)
Q1: Design a CMOS inverter to meet the following operating specifications: Inverter switching threshold voltge (VINV) = 2.2 V Output voltage rise time τrise = 5 nS when driving a capacitive load CL = 2 pf. nMOS and pMOS transistor channel lengths Ln = Lp = 1 um You may assume the following circuit and device parameter: VDD = +5 V; kn′ = μnCOX = 50 μAV2, kp′ = μpCOX = 20 μAV2; VT0(n) = 0.8 V, VT0(p) = −1 V a. What are the respective widths of the nMOS and pMOS transistors? b. What is the average propagation delay τp of the inverter? c. If the supply voltage is reduced to 3.3 V, determine the new switching threshold (VINV) and average propagation delay (τp) values of the inverter.
The outputs of two CMOS inverters are accidentally tied together, as shown in Figure below. What is the voltage at the common output node if the left inverter has a propagation delay of 1 ns while the right inverter has a propagation delay of 2 ns ? Assume that the two inputs are applied at the same time.
For the CMOS Inverter below, there is a kp is 2 mA/V2 and kn is double the value of kp respectfully. The threshold voltages for each MOSFET are Vtn = 0.5 V and Vtp = −0.5 V. Given Vin = 3.5 V and Vcc = 5 V, find the following parameters: Vout, rdsn, rdsp, IDn, and IDp.
A load CL is connected to the output of the CMOS inverter amplifier as shown in the mgure. Determine the high cut off frequency. Transistor parameters: |VT| = 1 V, λ = 0.01 V−1, and kn = 100 μA/V2, kp = 200 μA/V2 RF = 1 MΩ, CL = 60 pF. 28555 Hz 7615 Hz 19037 Hz None of them 38073 Hz 11422 Hz 22844 Hz 15229 Hz
Consider the CMOS inverter circuit below where k′n(W/L) = k′p(W/L) with (W/L)n = 20, (W/L)p = 40. K′n = 2 k′p = 20 μA/V2, Vt = |Vtp| = 1 V, C = 69.2 fF and VDD = 5 V. a) What is Vth? b) Draw the transfer characteristic in voltage c) Determine tp, tPHL and tPLH
Given (Fig. 1): Ln = 1 μm NMOS Lp = 1 μm PMOS Kn6 = 25 μA/V2 Kp6 = 10 μA/V2 tox = 69 nm, Cox = 5×10−4 pf/μm2 VTN = 1.0 V VTP = −1.0 V a) Determine the width of a NMOS transistor which draws 1.6 mA of current between drain and source when its Vgs = Vds = 5 Volts. (6 points) b) What is the corresponding W of the PMOS device if the gate is to have symmetrical delay characteristics? ( 4 points) c) This NMOS transistor is used as the pull down of an inverter loaded by an interconnect capacitance of 470 pf (Fig. 1). Calculate the time to discharge Vout from 5 Volts to 4.0 Volts, from 4.0 Volts to 0.5 Volts and from 5 Volts to 0.5 Volts. ( 25 points) Vout = 5 V at t = 0 Figure 1
A CMOS inverter, designed to have a mid-point voltage V1 equal to half of Vdd as shown in figure, has following parameters : Vdd = 3 V, μnCox = 100 μA/V2 Vtn = 0.7 V for NMOS μpCox = 40 μA/V2 Vtp = 0.9 V for PMOS The ratio of (WL)n to (WL)p is equal to (rounded off upto 3 decimal places).
For the CMOS inverter circuit shown below, assume the following: Kn′ = Kp′, Ln = Lp = 1 μm, and |VTP| = VTN = VT. Let's define the threshold as the point (vI = VTH) in the vO versus vI transfer curve where vO = VDD/2. a) Sketch the inverter transfer curve and mark the VTH point. b) Find an expression for the inverter threshold voltage VTH in terms of VDD, VT, Wn and Wp. c) If Wn = Wp, what is VTH ? In what mode of operation are M1 and M2 when VI = VTH ?
The CMOS inverter shown in Figure below has VDD = 1.8 V and is fabricated in a 0.18 μm process for which μn = 4 μp, μnCox = 400 μA/V2, and Vtn = −Vtp = 0.4 V. For this problem, neglect the Early effect. Both QN and QP use the minimum channel length allowed. For QN, W/L = 1.5. Find the width that QP must have in order for the inverter switching to occur at vI = 0.9 V. [15 points] (Hint: As vI = VDD/2, QN and QP are matched)
A CMOS inverter show below with all required parameters. kn′ = 100 μA/V2, VT0n = 0.75 v, kp′ = 40 μA/V2, VT0p = −0.8 v Vin (input voltage to the inverter) a. Calculate the inverter threshold VM ? ( 5 points) b. Explain the inverter regions of operation with respect to slowly rising ramp signal from logic "0" to logic "1" as shown in figure? , Explain clearly using the transfer characteristic of the inverter, the status of NMOS and PMOS when you increase the input voltage from 0 V to VTN and to VDD/2 and to VDD−VTn and VDD in time T. ( 15 points) c. When does NMOS and PMOS bias itself to saturation and why this is a danger in integrated circuit design. What are possible solutions to suppress this issue? (5 points)
b) The two-stage enhancement-mode metal-oxide field-effect transistor amplifier in Figure Q1 b has the parameters as follows: For NMOS: KN = 0.5 mA/V2, VTHN = 1 V, and λ = 0 V−1 For PMOS: KP = 0.5 mA/V2, VTHP = −1 V, and λ = 0 V−1 Determine the total voltage gain , AvT, of the multistage amplifier with the given load RL. Figure Q1 b
(a) For the circuit shown to the right, let vI go from VDD = 1 V to 0 V at t = 0. Before this transition, assume vo was 0.1 V. Write an expression for vo(t) for t > 0. (b) Let R = 10 kΩ and for the transistor, let kn′ = 0.5 mA/V2 and Vtn = 0.3 V. Derive the approximate (W/L) for the transistor so that vo = 0.1 V when vI = 1 V