Problem 3: (Short Circuit Power Consumption) For the circuit in Figure 2, assume that the input Vin is a periodic square wave signal (called "clock") of frequency 200 MHz, and has a rising transition time (from 0−100% of VDD ) of 0.2 ns and a falling transition time (from 100−0% of VDD ) of 0.2 ns. For the inverter in the figure, find the short circuit power consumption. Use the procedural hints listed below. Procedural Hints:Calculate the short circuit duration, tsc. Short circuit currents occur when both nMOS and pMOS transistors are simultaneously ON. Use the rise/fall times given. Calculate the peak short circuit currents. For simplicity assume that Ipeak_sc_LH and Ipeak_sc_HL are equal, and calculate the latter only. To calculate Ipeak_sc_HL, , assume that the short circuit current for the H-to-L transition peaks when Vin = VDD/2 and Vout = 9 VDD /10 (this is an arbitrary choice assumed for this problem alone). Now calculate the pMOS transistor current - this will be Ipeak_sc_HL. . Question: Does the nMOS current equal the pMOS current? If not, how do you account for InMOS−IpMO ? Using your results from (1) and (2), calculate the short circuit power dissipation. Note: Assume that VDD = 1.0 Volts, (W/L)p = 3.5 /0.1, and (W/L)n = 2 /0.1. Transistor properties are given by the 90 nm model parameters handout posted on the class web-site. For the current calculation, use the transistor parameters (not the equivalent resistance parameters) and ignore channel length modulation. Assume that there is an 89 fF load on Out.
Problem 1: (Dynamic Power Consumption) The NOR gate shown in Figure 1(a) is used in the two ways shown in Figure 1(b) and Figure 1(c). In both cases, the input, In, is a periodic square waveform with frequency 1 GHz. Assume VDD = 1.0 V. Use the simplified MOS RC model i. e. with Req, CGN', CGP' etc. (a) Calculate the dynamic power consumption for the circuit in Figure 1(b). (b) Calculate the dynamic power consumption for the circuit in Figure 1(c). Is it the same as in Figure 1(b)? Give reasons for your answer. Hint: Do not ignore the capacitance on node X. (8+12 = 20 points)
For the logic network shown below, μnCox = 115×10−6 A/V2, VTN = 0.43 V, μpCox = 30×10−6 V/A2, VTP = −0.4 V, VDD = 2.5 V. W/L = 1.5 μm/0.25 μm for MN1 and MN2. Neglect channel length modulation. What logic family does this circuit belong to? Determine the truth table and implemented logic function. Assuming the low and high voltage levels are 0 V and 2.5 V, determine the size of the PMOS so that VOL = 0.2 V What purpose does the PMOS serve in this circuit? What happens if it is removed? What are the advantages and disadvantages of this circuit versus the CMOS implementation with pull-up and pull-down networks?
The subthreshold behavior of an NMOS device is specified with Ioff = 100 pA and S = 100 mV/ decade. How much VGS does it need to conduct 10 nA subthreshold current for VDS≫Vth ? (a) 2 V. (b) 10 mV. (c) 100 mV (d) 0. (e) 200 mV. How much is the gate-source capacitance of an NMOS device in saturation for W = 10 μm, L = 0.4 μm ? (a) 30.6 fF. (b) 7.8 fF (c) 22.8 fF. (d) 228 fF. (e) 78 fF.
(10 points) Determine the Pass Transistor Logic input assignments that realize the Boolean Coincidence function Y = A⊙B ≡ AB + AB¯.
In which of the following conditions the current of an NMOS is absolutely zero? (a) VDS = 1.8 V, VGS = 0.3 V. (b) VDS = 0, VGS = 1.8 V. (c) VDS = 0.1 V, VGS = 0. (d) VDS = 0.5 V, VGS = 0.1 V. (e) VDS = 1.8 V, VGS = 1.8 V. Under which condition Ioff flows in an NMOS? (a) VDS = 0, VGS = 0. (b) VGS = 0.4 V, VDS = 0.4 V. (c) VS = 0.5 V, VD = 1.8 V, VG = 0.5 V (d) VGS = 0 V, VDS = 1.8 V. (e) VD = 1.1 V, VS = 1 V, VG = 1 V.
a) Discuss the advantages transmission gates have over the use of single NMOS and PMOS devices in pass transistor logic. ( 5 pts) b) Discuss the disadvantages transmission gates have over the use of single NMOS and PMOS devices in pass transistor logic. (5 pts) c) In the following transmission gate circuit, mistakes have been made by the designer. Correct the circuit diagram and write the appropriate Boolean expression for F. (10 pts)
(10 Points) Transmission Gate and Logic Design a) Consider the circuit shown in Figure 4, write in the node voltages at the intermediate and output nodes. For the NMOS transistor use a threshold voltage of Vtn = 0.5 V. (Note: Show your steps for getting full credit) Figure 4 Transmission gate based circuit b) What is the logical equation for the circuit shown Figure 5. Write the truth table accordingly. Figure 5 Combinational Circuit
Given VTN = 0.6 V, VA = VB = VC = 5 V and VI = 5 V. Ignore body effect Determine VO1 Choose Determine VO2 Choose Determine VO3 Choose.
Pass Transistor Logic VDD = 2.5 V(W/L)2 = 1.5 um/0.25 um (W/L)1 = 0.5 um/0.25 um (W/L)ni = 0.5 um/0.25 um kn′ = 115 uA/V2, kp′ = −30 uA/V2 VtN = 0.43 V, VtP = −0.4 V Figure 6.12 Level restoring circuit. Consider the circuit of Figure 6.12 . Assume the inverter switches ideally at VDD/2, neglect body effect, channel length modulation and all parasitic capacitance throughout this problem. a. What is the logic function performed by this circuit? b. Explain why this circuit has non-zero static dissipation. c. Using only just 1 transistor, design a fix so that there will not be any static power dissipation. Explain how you chose the size of the transistor. d. Implement the same circuit using transmission gates. e. Replace the pass-transistor network in Figure 6.12 with a pass transistor network that computes the following function: x = ABC at the node x. Assume you have the true and complementary versions of the three inputs A, B and C.
In the pass-transistor circuit shown below, all the NMOS transistors have a threshold voltage of 0.5 V and the body effect is ignored. The parasitic capacitances at nodes x, y and Out are all 20 fF. (a) When In = 0 V, find the voltages at nodes x, y and Out respectively. (b) When In = 2.5 V, find the voltages at nodes x, y and Out respectively. (c) Assume that the resistances of transistors M1, M2 and M3 are 8 kΩ, 15 kΩ and 8 kΩ respectively when they are turned on. When In changes from 2.5 V to 0 V, find the Elmore delay from In to Out. (d) Draw a pass-transistor-based 2-input XOR gate with no more than 6 transistors. Complementary inputs, if needed, must be generated within the circuit.
What is the logic function of these pass transistor or CMOS transmission gate circuits? These are additional ways of using pass transistors to implement logic functions. a) (10 pts) The A, A-bar, B, or B-bar signal is connected to the gate of the NMOS transistor in the CMOS transmission gate. The inverted signal is connected to the gate of the PMOS gate. b) (10 pts) The rectangles are pass transistors. c) (10 pts) Another example. Simplify the functions as much as possible.
The transmission gate shown above has the following parameters: kn′ = 100 μA/V2 kp′ = 40 μA/V2 VTN = |VTP| = VT VDD = 5 V VT0 = 1 Vγ = 0.5 V1/2 2ϕf = 0.6 V(W/L)P = 2(W/L)N = 2 a) Calculate VOH and VOL b) As the vi changes instantaneous from 0 V to VDD, Calculate iDN(0), iDP(0), iDN(tPLH), iDP(tPLH), and tPLH . iDP(tpH) ) and tpHL. d) Calculate tP.
The CMOS transmission gate shown has an input voltage of 1.0 V when it turns off. The W/L of the n-channel is 4 μm/0.6 μm and the W/L of the p-channel is 8 μm/0.6 μm. Estimate the change in output voltage due to clock feedthrough. You may assume the total parasitic capacitance between the output node and ground is 50 fF, that VDD = 3.3 V, and that the clock signal changes very fast. Ignore the changes due to overlap capacitance. Assume, VTN0 = 1.1 V, VTP0 = −1.2 V, Cox = 3.4 fF/μm2.
4*. In the circuit below KN = 0.1 mA/V2, KP = 0.1 mA/V2, |VTH| = 0.5 V, λN = λP = 0, neglect the body effect. a) At t = 0, the input voltage vi changes from 0 to 2.5 V. If the capacitor is initially uncharged, how long will it take for vo to reach 1.0 V. Assume VG and VGB are 2.5 V and 0 V respectively. b) If VG and VGB are switched to VG = 0, VGB = 2.5 V, both devices are off for midrange values of vi. Assume 0 < vo < 2.5 V. What is the lowest voltage that vi can become without one of the devices turning on?
What it does is this: when C is high, the transmission gate lets current pass from U to V in either direction; when C is low, the transmission gate chokes off the flow of current. That is, when C is high, U is connected to V; but when C is low, U is not connected to V. Question: what does the logic circuit below do? Write its truth table. Briefly briefly characterize or illuminate in words what the circuit does or what its function would be, preferably in no more than about 30 words.
Consider the following CMOS transmission gate. We want to estimate the 'rise time' for Vo(t) for a step input, Vin(t). The capacitor CL was initially uncharged. The device parameters are: kn = kp = 0.2 mA/V2, vtn = 1 V, vtp = −1 V. Neglect ro and body effect, and use CL = 1 pF. ( 45 pts) (a) Completing the following table by calculating the delay time (rise time) and sketch the waveform of vo(t). hint: What is the total charging current to CL ? ( 25 pts )
a) A transmission gate consists a pair of p-channel transistor and n-channel transistor connected in parallel, as shown in the following. Explain why a transmission gate is able to pass signals of 0 and VDD volts from A to B or vice versa when C = VDD equally well without any voltage loss. b) Describe how a 1-bit Flash Memory (shown below) store " 0 " or " 1 ". For the NAND Flash Memory below, given that "Ground Select Line" = Vdd and "Bit Select Line" = Vdd, what is the voltage required at "Word Line 0" and "Word Line 1" to read the state of Bit 0 ? Bit Line
For the pass-transistor circuit shown below, assume the following information: Vdd = 1 Vth = 300 mV γ = 0.4 V0.5 Kn′ = μnCox = 60 e−6 A/V2 |2φf| = 0.6 V W/L = 2 Calculate the output voltage Vout: A. Without body effect B. With body effect (you can use MATLAB to solve this problem) If you choose to use MATLAB, please turn in a copy of your code.
The figures below, represent a side view of a MOSFET with its channel under different operating conditions ( 6 marks) (a) (b) (c) (d) (e) a. Which of the figures above is the best representation of the channel in the schematic on the right (Choose one of (a) - (e)). Figure: b. Which of the figures above is the best representation of the channel in the schematic on the right (Choose one of (a) - (e)). Figure: c. Which of the figures above is the best representation of the channel of an NMOS transistor with VGS = 2.5 V, VDS = 2.3 V, VT = 0.7 V en VSB = 0 V (Choose one of (a) −(e)). Figure:
Problem 4 Transmission Gate. Figure 3 shows a transmission gate. Assume nfinn = nfinp = 2. Calculate the ON resistance of the transmission gate for the following bias values; (i) Vin = 1 V, Vout; 0 V, 0.5 V, and 1 V, (ii) Vin = 0.5 V, Vout = 0.5 V. Calculate parasitic capacitances at the input and the output. Figure 3 Transmission gate
Problem 3. a) Construct the gated D-latch with inputs D and G and outputs Q and Q _bar. The latch implements the following equation: Q∗ = GD+G′Q. One can use only inverters and transmission gates (TG). The TG transmits data with a high level on control input C. Show the schematic. b) Construct the D-flip-flop with negative edge triggering using Master-Slave approach. One can use only inverters and TG. The TG transmits data with a high level on control input C. The D-flip-flop has inputs D, CLOCK and outputs Q and Q_bar. Show the schematic. c) The D-latch and D-flip-flop circuits in parts a and b were tested with identical input signals. Clock was applied to the gate (G) input of the D-latch. Complete the waveform template. The initial state was unknown, assume negligible propagation delays. Q_flip-flop
P3.2. Consider the long-channel MOS device shown in Figure P3.2. At t = 0, the drain and source are at an initial voltage of 3.3 V. At t = 0+, the current source turns on with a value of 10 μA. On the graph, sketch the voltage at the source and drain nodes as a function of time until a steady-state behavior is reached. Estimate the voltages for the end points of every region of operation on the graph. Also, calculate the slope in every region. The key to this problem is to include the proper capacitances in each region of operation. For this problem, assume that k′ = μnCox = 180 μA/V2, VT0 = 0.6 V, VT = 1.1 V (Assume this is the correct threshold voltage when VBS is not 0 V ), and W = 1.5 μm, L = 1 μm (so the quadratic model can be used here). Use tox = 100Å to compute the gate capacitances. Assume CSB = CDB = 15 fF are fixed junction capacitances. Figure P3.2
QUESTION 1 Standard CMOS, pass-transistor logic, and dynamic logic each have advantages and disadvantages. Which of the following is/are not true in comparing these logic styles? A. Dynamic logic does not have a pull-up network. B. The area can be smaller for pass-transistor logic. C. Standard CMOS is best suited to complex circuits with many inputs. D. VOH is significantly lower than VDD in pass-transistor logic E. Dynamic logic is the most robust circuit style. F. Some logic functions can be implemented with fewer transistors in pass-transistor logic. QUESTION 2 All of the inputs swing between VDD and GND. A = L and B = L. The output voltage of this circuit is A. Vtn B. Cannot be determined C. 0 V D. VDD − Vtn E. VDD
Figure shows a circuit used to measure the effective value of body effect factor (γ) (by measuring VT at different source voltages) and channel length modulation factor (λ) (by measuring Id at different Vds values). Assume in formula for threshold voltage (slide 7 lecture set 4− MOS basics), 2φF = 0.88 V, and calculate VT0, γ, and λ for a device with 2 fingers. Can you justify the value of γ for the FinFET device you are simulating? Attach your CAD netlist, graphs and measurement data to your answers ( 25 points)
Pass transistor logic (25 pts) Consider the circuit shown in Fig. 1. Assume the inverter has balanced pull-up and pull-down strength. Neglect body effect, short channel effects and parasitic capacitance. VDD = 2.5 V. Assume all transistors in this question have the same size and W = 0.5 um, L = 0.25 um. Use the following parameters. a) (5) What is the logic function implemented by this circuit? b) (5) Identify the input pattern that will cause non-zero static power dissipation (when subthreshold leakage is ignored) for the inverter when inputs A and B are stable. Explain the cause of this static power consumption. c) (8) Compute the static power consumption for the input pattern identified in part b). Ignore subthreshold leakage. c) (7) Show two possible solutions each with 1 additional transistor to avoid static power consumption. Fig. 1
Shown is a positive latch built using transmission gates. Calculate the setup time, tsetup , and the propagation delay from the input D to the output Q, td−q. Use Cg = 2 fF/μm, Cd = 1 fF/μm and W = L = 2λ = 0.25 μm. Assume that equivalent resistance of NMOS transistor of width W is 13 kΩ and that equivalent resistance of PMOS transistor of width 2 W is 13 kΩ, that is use the following values for the transistor resistances: Rsq, n = 13 kΩ and Rsq, p = 26 kΩ.
[25%] Study the pass transistor logic below. Assume the inverter switches ideally at VDD/2. (a) What is the logic function performed by this circuit (at Out)? (b) Explain why this circuit has non-zero static power dissipation. (c) Using only one extra transistor, design a fix so that there will not be any static power dissipation. Explain how you choose the size of this transistor. (d) Replace the pass transistor network with a pass transistor network that computes the following function: x = A⊕B⊕C at the node x. Assume you have the true and complementary versions of inputs A, B and C.
VN is 0 V. vcontrolP Switches from 5 V to 0 V and stays at 0 V till capacitor settles to final value. d) Initial voltage condition on capacitor CL is 0 V. VN is 5 V. VcontrolP switches from 5 V to 0 V and stays at 0 V till capacitor settles to final value. e) Initial voltage condition on capacitor CL is 0 V. VN is 3 V. VcontrolN switches from 0 V to 5 V and stays at 5 V till capacitor settles to final value.
An NMOS device of Wdrawn = 0.3 μm, Ldrawn = 0.4 μm operates with VGS = 0.8 V and VDS = 0 V. How much is IN ? (a) 5 μA. (b) 12.5 μA. (c) 3 mA. (d) 0 . (e) None of the above. Which condition implies an NMOS device in saturation? (a) VGS = 1.2 V, VDS = 0 (b) VDS = 1.8 V, VGS = 1.8 V. (c) VGS = 0 V, VDS = 1.8 V. (d) VGS = 0.5 V, VDS = 0.5 V (e) VDS = 1 V, VGS = 1.8 V.