Consider the following circuit: (W/L)1 = (W/L)2 = 2 μnCox = 100 μA/V2 V Tn = 1 V λn = 0.05 V−1 (a) Find the DC Drain current Io such that the DC output voltage Vo = 3 V. You can ignore channel length modulation (i. e. λ = 0 ) for this part.
Problem 3: Consider the NMOS inverter with enhancement load driven by an NMOS transmission gate in the figure below. The threshold voltage of each n-channel transistor is VTN = 0.5 V. Neglect the body effect. Design the KD/KL of the inverter such that vo = 0.1 V when vI = 2.8 V and ϕ = 3.3 V.
For the pseudo NMOS circuit shown in Fig. 5, what is the output voltage and static power dissipation: a) if only one input is high? b) all four inputs are high? C) Compare analytically obtained results with SPICE simulations. Assume VDD = 2.5 V, Vtn = |Vtp| = 0.4 V.
Consider the NMOS inverter as shown in Figure 1.1. a) Design the circuit such that the power dissipation is 80 μW and the output voltage is vO = 0.06 V when vl is a logic 1. b) Used the result in part (a), determine the transition points for the driver and load transistor. c) If (W/L)D found in part (a) is doubled, what is the maximum power dissipation in the interver and what is vO when vl is a logic 1 Figure 1.1
A NMOS only inverter Figure 3 shows the design of an inverter with NMOS only. a. Simulate the maximum and minimum voltages at Vout . What's the corresponding Vin for them? b. Plot out the VTC. c. Compare this design with the CMOS inverter. What are the main disadvantages?
Consider the enhancement load NMOS inverter circuit given below. Circuit Parameters VDD = 5 V For both transistors VTN = VTL = 1 V KL = 10 μA/V2 KD = 40 μA/V2 a) Determine the transition voltage VI = VIt for the drive transistor. b) Complete the voltage truth table.
a) An NMOS inverter with depletion load is given on the right. Circuit Parameters VDD = 5 V, Transistor Parameters VTD = 1 V VTL = −1 V KNL = 25 μA/V2 KND = 100 μA/V2 The iD vs vDS behavior of the drive transistor is given below. The current has a linear behavior between 0 < vDS ≤ 4 V for VGS = 5 V. i. Draw the expected Voltage Transfer Characteristics (VTC) Vo vs VI. ii. Determine V0 L(min). iii. Determine the condition on V0 to set ML into SAT and MD into NONSAT when VI = 5 V. iv. Determine the noise margins. The NMOS transistor MD has the following idealized output characteristics.
Typical circuit parameters for the following questions: Consider the following Pseudo-NMOS inverter circuit. mn = 500 cm2/V-sec. μp = 250 cm2/V-sec. ε = 3.54×10−13 F/cm Tox = 5.0×10−6 cm Threshold voltage of NMOS transistors: Threshold voltage of PMOS transistors: Vth −1.0 V a) Draw input output curves (input on x-axis and output on y-axis) for 0 < Vin < Vdd (5 pts) b) Show regions of operation (cutoff, lin, sat) for both the p and n devices ( 5 pts) c) Derive Idd for all region of operations when devices are on only (15 pts) For example Ids = F(V Vin, . . ) when 1 v < Vin < 2 v
Problem 2. ( 50 points) Design a common-source amplifier with the circuit schematic shown below for the following specifications: Gain (Vout /Vin ) = 100, Output Swing = 0.1 V−2.9 V, and maximum power consumption of 1 mW. Assume VDD = 3 V and ignore body effect. (You need to find W/L of M1 and M2 transistors as well as DC voltage Vb and the DC component of Vin ). Draw the layout of this amplifier.
(b) The pMOS inverter above, contains one pMOS enhancement mode and one pMOS depletion mode transistor. You may assume that for a logic low input that both transistors are operating in their non-saturation mode. Calculate the voltage swing for this pMOS inverter, where VDD = 1.8 V, the enhancement threshold is exactly Vt = −0.4 V and the depletion threshold is exactly Vtd = 1.0 V, for the following pull-down (depletion) to pullup (enhancement) ratios: (i) 4:1 (ii) 8:1 You may assume that the input originates from a standard 8:1 pMOS inverter (i. e. an inverter with one enhancement mode and one depletion mode transistor).
Consider a saturated enhancement-load inverter such as the one shown in Figure 2. Figure 2. Saturated Enhancement-Load Inverter ⇒ Derive an expression for the theoretical value of VOH. The outcome is not a simple, elegant expression. You may leave it in terms of γ, |2ϕF|, and A, where A = VDD − VTO + γ |2ϕF|.
Question 1 (6): Consider a pseudo-NMOS inverter fabricated in 0.42−μm CMOS technology for which assuming λ1 = λ2 = 0, R = 1 K, Vtn = −Vtp = Vt, kn = 132 μA/V2, Vt = 0.5 V, VDD = 2 V, and kn = 2 kp. (a) Find VG, VO, ID when VI = OV and VI = VDD;
Consider a pseudo NMOS inverter shown below. Use the following equations for your calculations. Saturation region current-voltage equation: ID = 12 kp, n′p, nWL(VGS−VT0 p, n)2 Linear region current-voltage equation: ID = 12 kp, n′WL[2(VGS−VT0 p, n)VDS−VDS2] Transistor parameters: kp′ = μpcox = 55 uA/V2, kn′ = μncox = 100 uA/V2, VTN = 1 V, VTP = −1 V, WN = 12 u, LP = 1 u, LN = 1 u. Pseudo NMOS Inverter a) Find the value of WP if Vin = 5 V results in Vout = 0.25 V. b) Find the value of Vout if Vin switches from 5 V to 0 V. c) Find the value of the switching threshold voltage VM(Vin = Vout ). d) Derive an expression of the output capacitor in terms of CGS and CGD capacitors of the transistors.
Question 2. [6] A pseudo-NMOS inverter is shown in the figure below, with the process parameters shown next to the figure. a) [3] Find Vbias and (W/L)p, leading to equal rise and fall times, and VOL = 0.1 V. Explain your solution in detail. VDD = 1.2 V CL = 1 pF Cox = 8 fF/μm2 Vtn = |Vtp| = 0.3 Vμn = 3 μp = 0.06 m2 /Vs (W/L)n = 2 PA = 1 = 0.3 Vbias = (W/L)p = b) [2] Find the static power consumption of this circuit. Pstat = c) [1] Find the dynamic power consumption when input A is received from a system clocked at 1 GHz. (Hint: Pdyn = P1→0 fCLVDD(VDD−VOL)). Pdyn =
7.5 For the gate shown in Fig. P7.5, Pull-up transistor ratio is 5/5 Pull-down transistor ratios are 100/5 VTn = 0.53 V VTp = −0.51 V γ = 0.574 V1 /2 |2ΦF| = 1.020 V EC,pLp = 1.8 V a. Identify the worst-case input combination(s) for VOL. b. Calculate the worst-case value of VOL. (Assume that all pull-down transistors have the same body bias and initially, that VOL ≈ 5% VDD. ) Figure P7.5
VDD a) What is the purpose of C∞ at the gate of Q2 and the output? b) Where should the body terminal of Q2 be connected to in order to ensure there is no body effect? c) Express Rin . Assume ro = ∞ and there is no body effect. d) Express Rout . Assume ro < ∞ and there is no body effect. e) Express voltage gain. Assume r0 = ∞ and there is no body effect.
14.3 For a particular inverter design using a power supply VDD, VOL = 0.1VDD, VOH = 0.8VDD, VIL = 0.4VDD, and VIH = 0.6VDD. What are the noise margins? What is the width of the transition region? For a minimum noise margin of 1 V, what value of VDD is required?
The following circuit is improper (non-complementary) cMOS. Which of the following input combinations (a) ABC = 000 (b) ABC = 110 (c) ABC = 101 (d) ABC = 011 (e) ABC = 111
Consider a causal linear and time-invariant (LTI) system whose response to the input x(t) = e−tu(t) is the output y(t) = (e−t + 2te−t − e−2 t)u(t). (3 points) Find the frequency response H(jω) of the causal LTI system. (3 points) Determine the linear constant-coefficient differential equation relating the input and output of this causal LTI system. (3 points) Find the unit-impulse response h(t) of the causal LTI system. (2 points) Find the unit-step response s(t) of the causal LTI system.
Problem 3.3: In a particular cascoded current mirror, such as that shown in Fig. 3, all transistors have VTN = 0.6 V, kn′ = 200 μA/V2, L = 1 μm, and λ = 0.05 V−1. Width W1 = W3 = 2 μm, and W2 = W4 = 40 μm. The reference current IREF = 25 μA a) What output current results? b) What are the voltages at the gates of M2 and M4 ? c) What is the lowest voltage at the output for which current-source operation is possible? d) What are the values of gm and r0 of M2 and M4 ? e) What is the output resistance of the mirror?
Problem 3.4: Consider the Wide-Swing Current Mirror circuit in Fig. 4. Assume IREF = 50 μA and assume transistor parameters of VTN = 0.8 V, kn′ = 96 μA/V2, and λ = 0. a) Find (W/L) such that VDS(sat) = 0.2 V. b) What is VGS5 ? c) What is the minimum voltage at the drain of M1 such that all transistors remain biased in the saturation region?
Consider the current mirror shown below. a) What kind of current mirror is this? (2 points) b) Derive an equation for the small signal output resistance of this current mirror? Note that the output is at node B. (20 points) NOTE: You must show a full small signal model and all of your derivation starting from a KCL equation to get full credit for this. c) Derive an expression for the minimum DC voltage at the output. (8 points) d) Assume now that we apply a small signal vin at node A. What will happen to the voltage Vout. Hint: derive an expression for the voltage gain at node B. (20 points)
[20%] The circuit below is a BJT differential amplifier with VCC = VEE = 3 V. The DC current source IEE is assumed ideal. The two transistors are identical, operate in the active region, and have α = 0.99 and VA = ∞. The thermal voltage VT is 26 mV at room temperature. The input is purely differential, i. e. , vip = −vim = vid/2 a) Draw small-signal differential-mode half circuits of the differential amplifier. ( 5%) b) Express the differential voltage gain Ad, which is defined as (vop−vom)/vid, in terms of IEE, RL, α and VT⋅(6%) c) If IEE = 2 mA, what should be the value of RL to achieve Ad = 40 ? (4%) d) Choose another set of IEE and RL to maintain Ad = 40 while reducing the power consumption by half compared to the situation in part c). (2%) e) What is the maximum Ad that the circuit can achieve if the DC levels at the output nodes vop and vom must be equal to or higher than 0 V? (3%)
Consider the amplifier circuit shown below. Assume a transistor current gain of β = 120. The voltage VBB establishes the Q-point, and the voltage vi is a time-varying signal that produces a variation in the base current, which in turn produces a variation in the collector current and hence a variation in the output voltage vo. (a) Determine RB such that VCEQ = 1.6 V. (b) Determine the minimum and maximum input voltages, vi(min) and vi(max) such that the transistor does not enter cutoff or saturation and determine the corresponding output voltages vo(max) and vo(min) at these values of input voltage (c) What is the voltage gain Δvo/Δvi of the amplifier where Δvo≡vo(min) − vo(max) and Δvi ≡ vi(max) − vi(min) ? Assume VBE(on) = 0.7 V and VCE( sat ) = 0.2 V.
(20 pts) Q5. The following circuit is a ramp generator. Assume that OpAmp has an infinite gain and zero offset voltage. Also assume that OpAmp output can swing between Vcc and Vss. Let Vcc = 10 V VSS = −10 V, VS = 2 V, R = 1 kΩ, and C = 1 μF. a) Assume that switch is closed for t ≤ 0. After t ≥ 0 switch is periodically opened and closed with a period of T = 10 ms. Assume switch stays open for Topen = 8 ms and stays closed for Tclosed = 2 ms. Derive expression for Vo(t). Plot Vo(t) for two periods (i. e. 0 ≤ t ≤ 20 ms ). b) Realizing that this is not a pure ramp, Vs is adjusted. What value of Vs produces a pure ramp function with maximum peak value?
In Figure Q3, a voltage divider biased network for a CE amplifier circuit is shown. The transistor parameters are VBE(on) = 0.7 V, VCE(sat) = 0.2 V, β = 100, and VA = ∞. Figure Q3: CE Amplifier Bias Network (a) What is the advantage of emitter resistor RE ? (b) If VE is maintained at 1 V at the Q-point, estimate the maximum possible swing at the output terminal (vO). Justify your reasons. Determine a suitable DC value for collector voltage to be able to achieve the maximum swing. (c) What are VCEQ and ICQ ? (d) Determine values for R1 and R2. (e) A student has implemented this circuit on a breadboard to test the Q-point before applying AC input signal vI. Measurement results show that the collector voltage is equal to 25 V even though the values of R1, R2, and RE appear to be correct. What could be the reason(s) for this unexpected result? Explain where and what you would check in the circuit.
(10%) Determine the small-signal voltage gain (4%), the input resistance (3%), and the output resistance ( 3% ) of the amplifier shown in Fig. 2. Assume (W/L)M1 = 45/0.5, RD = 10 kΩ, Rs = 10 kΩ, RL = 100 kΩ, RF = 1 MΩ, VGS,M1 = 2 V. Use λ = γ = 0 for bias purpose and γ = 0, λ ≠ 0 for small signal analysis. Figure 2
In the cascode stage of Fig. 3 , assume that (W/L)1 = 50/0.5, (W/L)2 = 10/0.5, ID1 = ID2 = 0.5 mA, and RD = 1 kΩ. Use λ = γ = 0 for bias purpose and γ = 0, λ ≠ 0 for small signal analysis. (a) Choose Vb such that VDS of M1 is 50 mV away from the triode region. (2.5%) (b) Calculate the small-signal voltage gain Av = Vout Vin ⋅(2.5%) (c) Calculate the maximum output voltage swing using the value of Vb found in part (a). Which device enters the triode region first as Vout falls? (2.5%) (d) Calculate the swing at node X for the maximum output swing obtained above. (2.5%) Figure 3
In the circuit of figure below, assume that ISS = 1 mA and W/L = 50 /0.5 for all the transistors. (a) Determine the voltage gain. (b) Calculate Vb such that ID5 = ID6 = 0.8(ISS/2). (c) If ISS requires a minimum voltage of 0.4 V, what is the maximum differential output swing? VDD = 3 V, μnCox = 134 μA/V2, Vthn = 0.7 V, λn = 0.1 V−1 for L = 0.5 μm μpCox = 38.3 μA/V2, |Vthp| = 0.8 V, λp = 0.2 V−1 for L = 0.5 μm
Consider the emitter follower circuit below given VCC = 15 V, VEE = −15 V, RL = 1.3 kΩ, VBE,on = 0.7 V, VCE,sat = 0.2 V, and β = 100 for all the transistors. Find the value of resistor R in kΩ that will establish a bias current sufficiently large to allow the largest possible output voltage swing. Include the base currents for both Q2 and Q3. Please give your answer in two decimal places.
Consider a bipolar transistor amplifier: Assumptions: IS = 2.5×10−16 A, VT = 25 mV, VCE,sat = 0.2 V, β = 150, and the early voltage VA = 100 V Calculate the DC collector current Calculate RC such that the output experiences a maximum symmetrical swing Obtain the small-signal parameters of the circuit Calculate the voltage amplification ratio
(10%) Assuming that all the transistors in the circuits of Fig. 4 are saturated. Use λ = γ = 0 for bias purpose and γ = 0, λ ≠ 0 for small signal analysis. Calculate the small-signal differential voltage gain ADM = (Vout1 − Vout2 )/(Vin1 − Vin2 ) of each circuit. (R1 = R2) Derive the expression for ADM in terms of device parameters such as Rx, gmx, and rox. (a) (b) Figure 4
(10%) Please explain your answers clearly to the following questions. (a) Explain the concept of channel length modulation in NMOS and demonstrate its corresponding equation for drain current (IDs). (2%) (b) Elaborate on the body effect phenomenon in NMOS and present its corresponding equation for threshold voltage (VTH). (2%) (c) Write down the NMOS drain current equations for both the linear and saturation regions. ( 2% ) (d) Illustrate the complete small-signal model for NMOS, including all the capacitance terms. (4%)
(10%) Suppose the common-source stage of Fig. 1 is to provide an output swing from 1 V to 2.5 V. Assume that (W/L)M1 = 50 /0.5, RD = 2 kΩ, λ = γ = 0 for bias purpose and γ = 0, λ ≠ 0 for small signal analysis. (a) Calculate the input voltages that yield Vout = 1 V and Vout = 2.5 V⋅(3%) (b) Calculate the drain current and the transconductance of M1 for Vout = 1 V and Vout = 2.5 V. (3%) (c) How much does the small-signal gain for Vout = 1 V and Vout = 2.5 V. ? ( 4%) Figure 1
For the amplifier below assume: Kn = 200 uA/V2, VTN = 0.7 V Determine ID and Vin when Vo = 4.2 V. You may assume the transistor is in saturation. Determine Vo when Vin = 1.2 V. You may assume that the transistor is in saturation. Determine Vin when the transistor is in the onset of linear. Determine the Maximum output voltage. Determine the signal swing.
For the following Mosfet circuit sketch the Gain versus frequency response Showing the break frequencies at the low side of the spectrum due to capacitors at the gate, source, drain, and the internal capacitors Cgs and Cgd at the high of the frequency spectrum. Show all your work including the equivalent circuits to find the Equivalent resistances used to find the −3 dB frequencies If Vdd = 10 V, Vt = 1 mA/V, Vgs = 3 V, Id = 2 ma RG1 = 300 K, RG2 = 300 K, Rd = 1 K, Rs = 1 K, Rs1 = Rs2 2 = 500 Ω Low Freq Cg = 1 uF, Cs = 30 uF, Cd = 30 nF, high Freq Cgs = 15 pF, Cgd = 5 pF