Consider the circuit in the figure given below, where RD = 3.6 kΩ and VDD = 10 V. Determine the output voltage when the input voltage is high. Round the final answer to two decimal places. V
Consider the circuit given below, where RD = 680 Ω. Calculate the voltage across the E-MOSFET when VGS (on) = 2.5 V, RDS(on) = 10 Ω, and ID(on) = 100 mA. Round the final answer to two decimal places. V
Assuming (W/L)1 = 6, (W/L)2 = 2, (W/L)3 = 3, and (W/L)4 = 27, a reference current Iref = is required such that I0 = 9 μA. 27 μA 1 μA 3 μA 9 μA 6 μA
What is the minimum threshold voltage in millivolts that can be used for an NMOS FET to achieve an off current, loff, when Vgs = 0 V of no more than 0.78 nA per W/L at 300∘K ? Assume that this MOSFET has a steep retrograde body doping profile with a maximum depletion region thickness of Wdmax = 40 nm, and an effective oxide thickness, Toxe, of 22 angstroms. Use kT/q = 26 mV at 300∘K. Answer: The correct answer is: 147
If the threshold voltage for an NMOS FET with Vds = 893 mV rolls off by 101 mV as the channel length is decreased from 1 μm to 32 nm, then what is the DIBL characteristic length for this MOSFET in nanometers? Answer: The correct answer is: 12.6
What is the threshold voltage in millivolts for an NMOS FET with a source-to-body voltage, Vsb, of 612 mV ? Assume that this MOSFET has a steep retrograde body doping profile, with a maximum depletion region thickness of Wdmax = 39 nm. Also assume that this FET has an effective oxide thickness, Toxe, of 41 angstroms, and that it's threshold voltage with Vsb = 0 V is Vt0 = 476 mV. Use: kT/q = 26 mV and ni = 1.5×10^10 /cm^3 at 300∘K, εs = 11.7, ε0X = 3.9, ε0 = 8.854×10^−14 F/cm, and q = 1.6×10^−19 C. Answer: The correct answer is: 669
What is the minimum value of |Vds| that will keep a MOSFET in saturation in millivolts, for a PMOS FET with Vgs = −892 mV, and Vsb = 0 V ? Neglect the effects of velocity saturation, and assume that this MOSFET has a steep retrograde body doping profile with a maximum depletion region thickness of Wdmax = 40 nm. Use: W = 4.5 μm, L = 0.9 μm, Toxe = 31 angstroms, Vt = −482 mV, and μps = 112 cm^2/Vs. Answer: The correct answer is: 333
Q - 5: If Pseudo-NMOS techniques are used to build a 3-input NOR gate with W/Lp = 2.6 and W/Ln = 7.4, what will be its worst case (maximum) output low voltage, VOL, in millivolts? Use: VDD = 2.5 V, VTN = 0.4 V, VTP = −0.6 V, k'n = 150 μA/V^2, k′p = 60 μA/V^2
Assuming gm1 = gm2 = 0.5 mS, RC = 200 kΩ, RE = 300 kΩ, and VA1 = VA2 = ∞ the common mode gain Acm can be obtained as 50 V/V 100 V/V 0.66 V/V 0 V/V 0.33 V/V
For the BJT transistor circuit given in the Figure 3 below, Vcc = +10 V and the transistor's AC current gain, hFE = 250. Figure 3: BJT switching circuit a. Calculate the values of RB and RC that will ensure that the transistor operates efficiently as a switch for the input waveform Vin as shown above (use E12 resistor value). Sketch the output waveform that will result from the given input waveform. Use transistor DC gain, βDC = 250. [20 marks] b. Calculate the Q-point if a constant value of input voltage, Vin = 3 V is applied at the input. Determine if this design is feasible and, if it is not, suggest a solution to fix it? [10 marks]
Consider the common-source amplifier shown. The NMOS transistor has KP = 50 μA/V2, Vto = 2 V, λ = 0, L = 10 μm, and W = 400 μm. Find the midband voltage gain, input resistance, and output resistance of the amplifier. If the input source is given by v(t) = 100 sin(2000 Πt)mV compute the output voltage. Assume that the frequency of the source (which is 1000 Hz ) is in the midband region.
a) What is an operational amplifier (op-amp)? b) For the circuit given below, compute the output voltage, Uo as a function of the input signals. Describe the mathematical operation of this circuit and name this type of operational amplifier circuit. Assume that the op-amp is ideal. Figure 2: Amplifier circuit
Please consider a feedback amplifier system as seen Figure1. Let Gm = 10 mA/V, amplifier's input resistance ril = 100 kΩ, output resistance rol = 50 kΩ. Mosfet, Q, is biased to obtain gmQ = 1 mA/V and roQ = 50 kΩ. (70 points ) Figure 1 a) What is the topology? b) Please draw the AC equivalent circuit without feedback at midband frequencies, taking the loading of the feedback circuit into account. Clearly show the feedback signal on the circuit. c) Please calculate Ai = i0 /vs (without feedback) d) Please calculate β. e) Please calculate Af = io/vs. (with feedback) f) Please calculate fLf, the lower 3 dB frequency with feedback, if fL = 10 kHz.
A feedback amplifier circuit is shown in Figure Q4. Figure Q4: Feedback Amplifier (a) What type of feedback topology is used in this amplifier? (b) Redraw the amplifier circuit, replacing the op-amp with the equivalent circuit for this feedback topology. (c) Estimate the current, Io, the feedback gain, Aif in dB, and the amplitude of the AC voltage, vo, when RF = 150 kΩ, R1 = 4.7 kΩ, RL = 820 Ω, and Ii = 40 μAp−p at 1 kHz.
Figure shows a discrete-circuit CS amplifier employing the classical biasing scheme studied in Section 4.5. The input signal vsig is coupled to the gate through a very large capacitor (shown as infinite). The transistor source is connected to ground at signal frequencies via a very large capacitor (shown as infinite). The output voltage signal that develops at the drain is coupled to a load resistance via a very large capacitor (shown as infinite). a) If the transistor has Vt = 1 V, and k′nW/L = 2 mA/V2, and ID = 1 mA; verify that the circuit establishes VGS = 2 V, and VD = +7.5 V. (b) Find gm (c) Draw a complete small-signal equivalent circuit for the amplifier assuming all capacitors behave as short circuits at signal frequencies. (d) Find Rin, Vgs/ Vsig, vo/vgs, and vo/vsig.
Example 3: A shunt-shunt feedback amplifier is shown in Figure EX3. Assume the following specifications: gm = 40 mA/V RF = 33 kΩ rπ = 4 kΩ ro = ∞ (a) Determine the A-circuit. (b) Determine the input resistance Ri, the output resistance Ro, and the open-loop transresistance (A) of the A-circuit. (c) Determine the feedback factor β = If/Vo and the closed-loop gain Af. (d) Determine the input and output resistance of the feedback amplifier Rif and Rof, respectively. (e) Determine Rin and Rout . Figure EX2
The following amplifier faces gross distortion beyond the max power bandwidth point. Derive an equation describing such condition and sketch the max power-bandwidth curve ( w - Vin) as seen in the course slide. Also determine the size of the transistors to make Δ = 150 mV. Use C = 1 pF and A = 99, vthn,0 = 0.4 V, μnCox = 300 μA/V2, λn = 0.05 for hand calculations. Neglect body effect.
B) For the circuit in the following Figure. (20 points) a. Determine the following DC values for the amplifier: VB, VE, IE, IC, VC, VCE, re′ b. Determine the following values for the amplifier: Rin(base), Rin(tot), Rout, Av. c. Assume that a 600 Ω, 12 μV rms voltage source is driving the amplifier. Determine Av′ and the overall voltage gain by considering the attenuation in the base circuit and RL. d. Find the total output voltage. e. Draw the AC load line.
Figure Q2 shows a BJT differential amplifier stage that uses a tail resistor, RO, to provide a bias current, IQ. Transistor parameters are VBE(on) = 0.7 V, β = 100, and VA = ∞. Also, Vcc = 15 V, −VEE = −15 V, RO = 56 kΩ, and RC = 15 kΩ. Figure Q2: Differential Amplifier (a) To calculate the transistor Q-points, what are the values you would assume for vB1 and vB2 ? (b) Determine the bias currents, IC1 and IC2, of the amplifier. (c) For a single-sided output, determine the differential-mode voltage gain (Ad), the commonmode voltage gain (Acm), the differential input impedance (Rid), the common-mode input impedance (Ricm), and the common-mode rejection ratio (CMRR) in dB for the differential amplifier. Assume a signal source resistance of 50 Ω on each input. (d) Will changing RC affect the amplifier CMRR? (e) Suggest two changes to this amplifier each of which would allow the CMRR to be increased. For each, give a reason why the change would have the desired effect.
Problem 6(10%): The circuit below is a partial circuit design for an amplifier. The output at A is rated to be 3 V when the input is 1 mA. α is equal to 5 V/mA. Design an interface circuit that will meet these conditions.
Consider the circuit below where R = 10/3 Ω, L = 5 H, and C = 0.1 F. a)Find the transfer function H(s) = OUT(s)/IN(s) and the impulse response h(t). b)Find the zero input response at out( t ) when the inductor has an initial current from top to bottom; iL(0) = 0.1 A. There is zero initial charge on the capacitor.
Question 2. Consider the circuit to the right. Let VDD = VSS = 5 V, RD = 2 kΩ, and I = 2 mA. The transistors are matched with kn = 0.5 mA/V2 and Vtn = 0.4 V. Let the transistor gate voltages be 2 V. (a) Derive the voltages at the transistor drains (b) Derive the voltages at the transistor sources
Problem 3 [20 points]: For the circuit below, assume R = 3 Ω, L = 2 H, C = 1 24 F, and A = 12 V. Find the capacitor current ic(t), t ≥ 0 using the Laplace transformation method.
Consider the RLC circuit shown in Figure E1. The switch S is closed at t = 0. Determine the instantaneous current at t = 0.4 s, given, R = 2 Ω, L = 0.2 H, C = 5/9 F, V = 200 V. Plot the current wave form. If the value of the capacitance is changed to 0.5 mF sketch the resulting waveform. Figure E1: Circuit for Exercise 1. i(0.4 s) = 80.37 A
You are told to find the transfer function of the following circuit. You know that the transfer function will take the form H(ω) = jA/(R+jB), where A and B are variables that depend on component values and the input signal frequency. Find the value of B, given the following values: R = 2 kΩ, L = 9.1 mH, C = 559 μF, ω = 2,392 rad/s. Please enter the answer to 3 significant figures.
Find the transfer function of the following system G(s) = IR(s) Ii(s). (20 Points)Assume L = 1 H and C = 4 F. (40 Points) a) Find the values of R that generates different system responses to the unit step input such as "overdamped, underdamped, critically damped and undamped". (10 Points) b) Define the corresponding transfer function, of previous part, in MATLAB for each case. (10 Points) c) For each case, plot pole and zero locations and step system response of the system in a single figure using subplot. (10 Points) d) Redo the simulation in MATLAB Simulink and show the results in a scope. (10 Points)
Consider that GM = KM = 1, GP = K/(τ1s+1), and GD = KD/(τ1s+1). a) Write the transfer function for a setpoint change, Y′(s)/Ysp′(s), given that GC1 = K1, GC2 = K1 /τIs and GC3 = K1τDs. b) Write the transfer function for a setpoint change, Y′(s)/Ysp′(s), given that GC1 = K1, GC2 = K1 and GC3 = K1(1 + τDs)(1 + 1/τIs). c) Consider the following values: τ1 = 2, τI = 1, τD = 5, K1 = 3, K = 2. Write the expressions and plot (not sketch!) the response for both system a) and system b) to a step change of Ysp′ = S(t).
A process with transfer function G(s) = 1 (s+2)(s+4) is cascaded with a controller D(s) = K(1 + 8s), K > 0, in a unity feedback loop. (a)Draw a neat sketch of the root locus showing all its important features. (b)It is required to locate the furthest pole of the closed loop at -5 , find the value of K and calculate the value of the frequency of oscillations in the time response. (c) Find the value of K that results in multiple poles of the closed loop.
(a) Using Routh test determine if the system shown in Figure Q6 will be stable when: G1(s) = H1(s) = 2 G2(s) = 1 2s+2 H2(s) = 3 s2+3 (b) Discuss how an appropriate Bode plot can be used to determine if the closed-loop system shown in Figure Q6 stable or not. What transfer function should be used to generate this Bode plot?
Problem 7. For the feedback control system given in the figure on the right, (a) Find the closed-loop transfer function, C(s)/R(s). (b) Determine the system's stability range for gain K using Routh-Hurwitz criterion. (c) What is the type of the system? (You need to convert the system to a simple unity feedback. ) (d) Sketch the root-locus in Matlab (you need to use the open-loop transfer function with K = 1 ) and validate the stability region you found in (b). (e) Plot the step response up to 10 seconds for the input of 1.5u(t) and the gain value that makes the system marginally stable. (f) Find the steady-state error for an input step of 1.5u(t) for K = 22 and plot this response together with the input up to 10 seconds in order to display the steady-state error you computed. (g) Find the steady-state error for an input ramp of 1.5tu(t) for K = 22 and plot this response together with the input up to 10 seconds in order to indicate the steady-state error you computed.
Question 1: An aircraft landing/takeoff system block diagram is demonstrated below. For the given system find the following : a) Using Routh-Hurwitz array, find the range of gain K for which system is stable ? b) Using Routh-Hurwitz array, find the value of gain K for which system is marginally stable? c) The poles of system for the value of K for which system is marginally stable?
(c) The closed-loop block diagram of an active suspension system is depicted in Figure 3. Let R(s) and Y(s) be the input and output variables, respectively. (i) Determine the system's characteristic equation. (ii) From the characteristic equation, construct the Routh array. (iii) Determine the range of K so that the system is to remain stable. (iv) Compute the frequency at which the system is marginally stable.
The original system above (Fig. 2-2) is now proposed to be equipped with an integrator placed in the forward path to reduce steady state errors due to high order control inputs. Answer the following questions a) - c). Fig. 2-2 Hydraulic position control system for a roll stabiliser fin with an integrator a) Determine the new stability margins for the modified system (4 marks) b) Sketch the possible pole locations for the modified system (2 marks) c) Apply the Routh array to this system and comment on the results. (2 marks)
Consider a feedback control system with a closed-loop transfer function of the form T(s) = P(s) Q(s); Q(s) = s3 + 4s2 + 6s + 4 (a) Determine, via mental / manual efforts, the roots of Q(s) [i. e., the poles of T(s). ] (5 points). (b) Then, construct / generate a Routh Table (RT) for Q(s) and qualitatively confirm the results obtained from the first task. (5 points)
P5: The transfer function of a filter circuit T(s) is given by: T(s) = 100 s/ω0B (s/ω0A + 1)(s/ω0B + 1)ω0A = 104 rad sec ω0B = 400 rad sec a) Sketch its asymptotic Bode plot, magnitude only b) What type of filter is it? c) What is its exact gain at 2000 rad/sec ?
The circuit below is a high-pass filter. The designer intends to obtain a high-frequency gain of 40 dB, a corner frequency w1 of 100 rad/sec, and an input impedance of ∼2.5 kΩ at high frequencies ( > > w1). a) Determine the values of C1, R1, and R2 to obtain the above specifications. b) Draft the Bode plot of the voltage gain, magnitude only.
A recent trend has been to augment a linear controller with another more advanced controller. This is often accomplished by decomposing the control input u(t) = u1(t)+u2(t) into a control signal u1(t) from a traditional linear controller C(s) and a control signal u2(t) from an advanced nonlinear controller e. g. a neural network. The resulting block diagram is shown below. (a) (2 points) Find the closed-loop transfer functions from r(t) and u2(t) to output y(t). (b) (4 points) Use MATLAB to plot the Bode plots for the closed-loop transfer functions where P(s) = 1 s2+4s+5 and C(s) = 10s2+20s+10 s2 From the Bode plots, is adding a neural network controller a good idea?
Question 1 (20 points, Amplitude Modulation): We are given the following signal in frequency domain (Fig. 1), Figure 1: Message signal in frequency domain. (a) (10 Pts.) Draw the spectrum for the SSB modulated signal. Show how we recover the original signal through a receiver architecture? (b) (10 Pts.) Repeat Part a, for the VSB modulation.
The modulation process of a scheme called vestigial sideband (VSB) modulation is shown in Figure (a) and BPF response is given in Figure (b). Show that the message signal m(t) can be demodulated by the same coherent detector used in DSB-SC. (25 pts)
Consider the following problems related to the modulation and power properties of the Fourier transform. (a) The carrier of an AM system is cos(10t), consider the following message signals i. m(t) = cos(t) ii. m(t) = r(t) − 2r(t−1) + r(t−2), where r(t) = tu(t) Sketch the modulated signals y(t) = m(t)cos(10t) for these two messages and find their corresponding spectrum. (b) Find the power Px of a sinc signal x(t) = sin(0.5t)/(πt), i. e. , the integral Px = ∫−∞∞ |x(t)|2 dt
The below message signal is transmitted as an angle-modulated signal. The modulation system has ωc = 20π×106 rad/s. a) Let kf = 200000π. Sketch the frequency-modulated signal φFM(t) in the time domain. b) Let kP = 50π. Sketch the phase-modulated signal φPM(t) in the time domain. Write the frequency details in your sketch.
The baseband signal m(t) is as follows. DSB-TC is modulated to transmit a signal of sm(t) = [m(t) + Ac]cos(20πt). However, T0 = 1 sec. (1) Draw a waveform of sm(t) when Ac = 1.2 (2) Draw a size spectrum of sm(t) when Ac = 1.2 (3) Find the modulation index μ when Ac = 2 (4) What is the power efficiency of η when Ac = 2 (5) What is the minimum value of Ac and the maximum power efficiency at this time when envelope detection is possible? (6) Draw the waveform of the detector output signal when sm(t) is entered into the envelope detector.
Question 3: In the DSB-SC modulator of Figure 1, the carrier is cosωct and the message signal is m(t) = 4 cosωmt + 2sin3ωmt, where ωm = 5π×103 rad/s and ωc = 2π×104 rad/s. The modulated signal is used as the input signal of the demodulator of Figure 2, in which the carrier is 2cosωct and the lowpass filter bandwidth is 20 kHz. Find an expression for x(t) of Figure 2 and for yd(t), the output signal of the demodulator.
P3: In an amplitude modulation system, the message signal is the periodic square wave shown below and the carrier frequency is 1 kHz. The modulator output is xAM(t) = 2[b+0.5 m(t)]cosωct (a) Determine the average power in xAM(t) as a function of b and A. (b) If b = A, determine the modulation index and the modulation power efficiency. (c) Find the minimum value of b such that the AM signal can still be demodulated via envelope detection. Determine maximum modulation index and maximum modulation power efficiency based on the resulting b.
P2: Sketch the AM signal [A+m(t)]cosωct for the signal m(t) shown below corresponding to the modulation index by selecting a corresponding A assuming a carrier frequency of 80 Hz : (a) μ = 0.5 (b) μ = 1, what is the bandwidth of the modulated signal (c) μ = 2. Draw the positive envelope. (d) μ = ∞. What is the bandwidth of the modulated signal
3.14 The signal m(t) = {t, 0 ≤ t < 1 −t+2, 1 < t ≤ 2 0.1 otherwise frequency-modulates a carrier with frequency 1000 Hz. . The deviation constant is kf = 25. a. Determine the range of the instantaneous frequency of the modulated signal. b. Determine the bandwidth of the modulated signal. c. Plot spectra of the message and the modulated signal. d. Determine the modulation index.
Suppose an LTI system with impulse response h(t) has frequency response H(ω) shown below: What is the following equal to: ∫−∞∞ (∫−∞∞ h(τ)h(t−τ)dτ) e−jtdt None of these 6 1 2 1/π 12 0 8 3 11 4 2π
b) The circuit shown in Figure 3-1 is used in the design of a high frequency oscillator. Assume that all components are ideal and that R1 = R2 = 10 Ω, R3 = R4 = 10 kΩ, C = 10 nF and L = 1 μH. Figure 3-1. Oscillator circuit i) Using the Barkhausen criteria show that this circuit will function as an oscillator. ii) Determine the oscillation frequency.
a) What is the voltage gain of the common-source amplifier shown below? Assume Kn = 0.45 mA/V2, VTN = 1 V, and λ = 0.0133 V−1. b) What is the maximum value of vi that satisfies the small-signal assumptions? c) Compare the voltage gain to the common-source "rule-of-thumb" gain estimate and the "intrinsic gain" of the transistor.
The current gain of an amplifier is 500, the load resistance is 100 Ω, and the input resistance of the amplifier is 1 MΩ. Determine the voltage gain and power gain under these conditions.
Select the Boolean expression for the following circuit. Note that the bar at the top represents Vdd Y = A′B′+C Y = (A+B)C Y = (A′+B′)C′ Y = AB+C None of the options
For the given differential amplifier, calculate the output resistance Rout and the differential gain Aid = V0/Vid. Assume: I = 30 μA (W/L)1 = (W/L)2 (W/L)6 = 4⋅(W/L)4 (W/L)5 = 4⋅(W/L)3 (W/L)8 = (W/L)7 gm1 = gm2 = 100 mS λn = λp = 0.04 V−1 Rout = kΩ Aid = V/V
In the dynamic logic circuit shown below, all the transistors have the minimum channel length, and their sizes (widths) are marked. The inverter at the output is a standard static CMOS inverter with a PMOS size of 2 and an NMOS size of 1 . For a unit-sized NMOS or PMOS transistor, the intrinsic capacitance at its drain or source terminal is CD, and the capacitance at its gate is CG. For unit-sized NMOS and PMOS transistors, their onresistances are RN and RP, respectively. CD = CG = 1 fF and RP = 2 RN = 2 kΩ. (a) Express y as a Boolean function of the inputs A, B, C and D in the evaluation phase (CLK = 1). (b) Find the capacitances at nodes y, a, b and c, respectively. (c) Let A = B = D = 1 and C = 0 and suppose nodes a, b and c are at 0 V in the pre-charge phase (CLK = 0). Estimate the time it takes for the voltage at y to decrease from VDD to VDD/2 in the evaluation phase. (d) Repeat (c) if nodes a, b and c are at VDD in the pre-charge phase. (e) If the inputs are C = 1 and A = B = D = 0 and suppose nodes a, b and c are at 0 V in the pre-charge phase. Considering the charge sharing effect, what is the voltage at node y in the evaluation phase? It is known VDD = 2.5 V, VTN = 0.5 V and the body effect of the transistors can be ignored.
An N-MOSFET is fabricated using a 0.18 μm technology (minimum channel length Lmin = 0.18 μm.) It's kn′ = 387 μA/V2 and VA′ = 5 V/μm. For the basic amplifier cell that is biased by a current source, as shown in the following circuit, it's required to obtain an intrinsic gain ( vd/vi in the circuit) of 25 V/V and a gm of 1 mA/V. Assuming the overdrive voltage in the system is VoV = 0.2 V, find the required values of L, W/L, and the bias current I of the cell. (Note: the Early voltage VA can be given in the format of VA′ - Early voltage per unit channel length. Therefore, VA = VA′⋅L.)
Question 3. The MOS differential amplifier shown in the figure utilizes a pair of matched PMOS transistors for which Vtp = −0.4 V, kp = 100 μA/V2, and W/L = 50. Channel length modulation can be neglected. a. For an input common mode voltage VCM within the input common mode range of the amplifier, what are the dc voltages at the drains? b. Find the input common mode range assuming that for proper operation the bias current source requires a minimum voltage across it of 0.2 V. c. What is the input differential voltage (vG1 − vG2) that steers the bias current entirely into Q1 ?
Current Mirrors (35 points) This problem introduces current mirrors, which will be covered in more details in future lectures. Consider the circuit shown below (Figure 2). (W/L)1 = 1, (W/L)2 = 5, Rref = 50 kΩ, ignore channel length modulation unless otherwise stated. Assume L1 = L2 = 1 μm. Figure 2 a) (5 points) Assume RL = 10 kΩ. Calculate IL, the current flowing through RL. What is the current mirroring ratio ( IL over Iref , where Iref is the current through Rref )? We want the current mirror to provide a load-independent current as much as possible, so check that M2 is in saturation. b) (5 points) Determine the maximum RL and minimum VOut such that the current mirror still functions with the same current mirroring ratio you calculated in part a). Hint: for the current mirror to function as desired, transistor saturation should be maintained. c) (5 points) Channel length modulation introduces load-dependent errors in the mirroring ratio. Using λ = 0.1 V−1 for L = 1 μm, estimate the percentage error in the mirroring ratio. Here, set RL to its maximum value you got in part b ), and assume that we want the same IL as in parts a) and b). Hint: what should be the new VX and Iref ? d) (4 points) Compute the output resistance, Rout, , looking into the drain of M2. Use λ = 0.1 V−1 and assume the same IL as in parts a) through c). e) (5 points) Now consider redesigning the previous current mirror with source-degenerated transistors as shown in Figure 3. Ignore channel length modulation and body effect ( Assume bulk is tied to source). Transistor sizes remain the same, (WL)1 = 1 and (WL)2 = 5. This circuit has been designed to have the same Iref as in part a). What should the value of Rs2 be if we want the same current mirroring ratio as in a)? f) (5 points) Similarly to part b, determine the maximum RL and minimum VOut such that the current mirror still functions with the same current mirroring ratio as in part e). g) (4 points) Now compute the output resistance, Rout , looking into the drain of M2 (using λ = 0.1 V−1 ). Assume IL as used in parts e) and f ). h) (2 points) Comparing the minimum output voltage and the output resistance of these two current mirrors, comment on the advantages and disadvantages of using source degeneration in a current mirror. Figure 3
Consider the following structure of dynamic MOS logic circuits. Assume that the minimum size of NMOS is 2 units (n = 2) and PMOS is 3 units (p = 3) with channel length of 0.15 μm(L = 0.15 μm). Determine the minimal channel width (in μm) of each of the transistor below, so that the logic is operational. (30%)
Problem 5.5(a): An NMOS transistor fabricated in a technology for which kn′ = 511 μA/V2 and Vt = 0.4 V. It is required to operate with a small VDS as a variable resistor by varying the control voltage, VGS, from 0.5 V to 1.0 V. The transistor has the minimum channel length for this technology, Lmin = 0.130 μm. Specify the transistor width, W[ in μm], required to achieve a minimum resistance of 0.3 kΩ.
An amplifier has an input resistance of 40 kΩ, an output resistance of 100 Ω, and a short-circuit current gain of 120,000 A/A. The amplifier is connected to a source voltage of 50 mV with a source resistance of Rs = 10 kΩ. The output of the amplifier is connected to a load resistance of 220 Ω. (a) Find current gain, Ai = io ii. (b) Find the voltage gain, Av = vo vi. (c) Find the voltage gain from source to load, Avs = vL vs. (d) Find the power gain, AP = PL PI.
The current gain of an amplifier is 500, the load resistance is 100 Ω, and the input resistance of the amplifier is 1 MΩ. Determine the voltage gain and power gain under these conditions. Select one: a. Av = 0.05 and G = 50 b. Av = 0.025 and G = 25 c. Av = 0.025 and G = 50 d. Av = 0.05 and G = 25 e. None of the answers
A certain amplifier has an input voltage of 100 mV rms, an input resistance of 100 kohms, and produces an output voltage of 10 V rms across an 8 ohms load resistance. The power supply has a voltage of 15 V and delivers an average current of 2 A. Find the power dissipated in the amplifier and the efficiency of the amplifier. Select one: a. Pd = 10 W and Eff = 41.7% b. Pd = 30 W and Eff = 20% c. Pd = 17.5 W and Eff = 41.7% d. Pd = 17.5 W and Eff = 35.4% e. None of the answers
Given the amplifiers A and B described below, find the input impedance, output impedance, and open-circuit voltage gain of the cascade A-B. Amplifier Open-circuit voltage gain Input resistance Output Resistance A 100 3kΩ 400Ω B 100 1MΩ 2kΩ Select one: a. Ri = 1 Mohms, Ro = 400 hms, and Avoc = 24990 b. Ri = 3 Kohms, Ro = 2 Kohms, and Avoc = 49980 c. Ri = 3 Kohms, Ro = 2 Kohms, and Avoc = 35800 d. Ri = 1 Mohms, Ro = 400 ohms, and Avoc = 54090 e. None of the answers
What is the minimum channel length in nanometers that can be used to achieve an intrinsic voltage gain of at least 86 V/V in a CMOS process with a DIBL characteristic length of 15.2 nm? Answer: The correct answer is: 67.7
What is the intrinsic voltage gain in V/V for a MOSFET with L = 35 nm in a CMOS process with a DIBL characteristic length of 17.1 nm ? Answer: Check
If the DIBL characteristic length is 29.1 nm for a CMOS process with Toxe = 27 Å, Wdmax = 56 nm, and Xj = 64 nm, then what will the new value of the DIBL characteristic length be in nanometers if Toxe is scaled down (reduced) by 54.3% ?
If the DIBL characteristic length for a MOS process is 19.9 nm, then what will the threshold voltage be in millivolts for a PMOS FET with a channel length of 37 nm at Vds = −812 mV ? Assume that the threshold voltage is −277 mV for long channel lengths. Answer: The correct answer is: -88