Electrical Engineering Archive: Questions from 2024-05-19

In the following AC circuit, the voltage generator E has a peak-to-peak value of 170 V and a frequency of 50 Hz. Therefore, compute the value of C needed to achieve total power factor correction, knowing that ZL is an inductive load absorbing an active power of P = 10 kW with power factor cos⁡(φ) = 0.7 (a) C ≈ 1.4 mF c. (b) C ≈ 2.5 mF (c) C ≈ 1.9 mF o (d) C ≈ 1.7 mF

Problem 1: Consider a MOS amplifier incorporating the resistive-divider biasing circuit with source degeneration RG1 = RG2 = 10 kΩ μnCox = 400 μA/V2 VDD = 4.0 V VTH = 0.4 V W/L = 28 μm/280 nm RD = 500 Ω RS = 20 Ω λ = 0.08 V−1 Question 1: Calculate the drain current assuming M1 to be in saturation Fig. 1 Question 2: Calculate voltage gain

9.98 For the BiCMOS differential amplifier in Fig. P9.98 let VDD = VSS = 3 V, I = 0.2 mA, kp′W/L = 6.4 mA/V2; |VA| for p-channel MOSFETs is 10 V, |VA| for npn transistors is 30 V. Find Gmd, Ro, and Ad.

For the NMOS inverter with depletion load assume VDD = 5 V, VT1 = 1 V, and VTL = −1.2 V. For Vin = 0.63, VDG2 is a. 0.25 b. 4.00 c. 5.00 d. 0.00

The drawing below shows a cross section of a very long thin conducting plane of width w = 3.5 mm that is carrying a uniformly distributed total current I = 7.1 A into the page. What is the magnitude of the magnetic field (in milli-Tesla) at point P in the plane of the ribbon at a distance d = w/2 from its edge?

For the NMOS inverter with depletion load. Assume VDD = 5 V, VTD = 1 V, KD = 81.1 μA/V2, VTL = −2 V and KL = 27.8 μA/V2. If VOH = 5 V, VOL = 0.17 V and the input is switched from high to low logic at t = 0, then for t > 0, the charging current (μA) for the load capacitor when Vo = 2.4 is a. 101.19 b. 1089.98 c. 111.20 d. 1297.60

For the CMOS inverter shown assume Vss = 5 V, Assume VTn = 1 V, Kn = 51.8 μA/V2, VTp = −1.5, Kp = 22.9 μA/V2. At t = 0, the input is switched from low to high logic, then for t > 0, the current Ic (μA) when Vo = 2.7 V is a. -828.80 b. -280.52 c. -741.26 d. -247.55

Assume all transistors are operating in saturation and λ = 0. (a) Sketch, in the same graph, ID1 and ID2 versus Vin1 − Vin2 (b) For what value of Vin1 − Vin2 are ID1 and ID2 equal? Show the point in the graph of part (a).

7.75. The source follower of Fig. 7.97 employs a bias current source, M2. (a) What value of Vin places M2 at the edge of saturation? (b) What value of Vin places M1 at the edge of saturation? (c) Determine the voltage gain if Vin has a dc value of 1.5 V. (d) What is the change in the gain if Vb changes by ±50 mV ? Figure 7.97 In the following problems, unless otherwise stated, assume μnCox = 200 μA/V2, μpCox = 100 μA/V2, λ = 0, and VTH = 0.4 V for NMOS devices and −0.4 V for PMOS devices.

77. Consider the CS stage shown in Fig. 7.99, where M2 operates as a resistor. Figure 7.99 (a) Determine W2 such that an input dc level of 0.8 V yields an output dc level of 1 V. What is the voltage gain under these conditions? (b) What is the change in the gain if the mobility of the NMOS device varies by ±10% ? Can you explain this result using the expressions derived in Chapter 6 for the transconductance? In the following problems, unless otherwise stated, assume μnCox = 200 μA/V2, μpCox = 100 μA/V2, λ = 0, and VTH = 0.4 V for NMOS devices and −0.4 V for PMOS devices.

For the two-stage amplifier above, RG1 = 300 Kohm, RD1 = 23 Kohm, Rs1 = 2 Kohm, gm1 = 0.7 mS for M1 and C2 is used for dominant pole. To design the lower corner frequency fL = 3.6 KHz, determine the value of C2 in nF

Q3: RC Energy Model When applying a step input (with Vin going from VDD to 0 ) to a CMOS inverter, an amount of energy is provided by the power source. How much energy is delivered by the power supply? How much energy is stored in the capacitor? (Assume NMOS/PMOS equivalent R = 1 kohm, CL = 1 nF )

Q3: Logic Effort The logic path below needs to drive CL, you are free to add buffers. In order to minimize path delay, please decide the optimal number of stages, and the PMOS and NMOS sizing of A, B, C. (CL = 86 Cunit. . RP = 2 RN.)

(ii) For the common source amplifier shown in figure 1(b) determine the 3 dB frequency, given the following values for the components: RD = 10 kΩ, RL = 10 kΩ, R1 = 50 Ω, the MOSFET gate source capacitance, Cgs = 10 pF, the MOSFET gate drain capacitance, Cgd = 10 pF. Assume that the MOSFET drain current, ID = 0.2 mA and that the MOSFET is operating in the saturation region. Neglect the effect of channel length modulation. Figure 1(b) Answer: fc = 1 2π(Cgs + Ceq)R1 Ceq = 91.9 pF

An RF amplifier is designed by a MOSFET at 2.4 GHz for Wi-Fi applications. The S-parameters of the transistor are shown below. (a) Based on z-parameters, determine the new [S] matrix with a 0.5 nH inductor Ls connected to the source terminal as the inductive source degeneration for improved matching. ( 10 /100) (b) With LS connected, another inductor LD connected to the drain is used for inductive peaking, often used to increase the high-frequency gain. Based on ABCD parameters, determine the overall [S] matrix of the amplifier if LD is 1.5 nH. (10/100) (a) (b) S11 = 0.7∠−45∘S12 = 0.12∠45∘S21 = 5.8∠120∘S22 = 0.5∠−30∘

Figure 1(a) shows a BJT based current mirror where the BJT current equation is given by: IC = IS′AEe VBE VT(1 + VCE VA) where Is′ = 50 fA, AE is normalized emitter area, thermal voltage VT = 25 mV and early voltage VA → ∞. Further, it is given that IREF = 0.5 mA, Vdd = 5 V and β = 50 for both Q1 and Q2. (a) Derive the equation of mirror ratio MR = Io/IREF. Using this, find Io, VBEI and VCEI if AE1 = 2, AE2 = 2. (25 Marks) (b) Suppose I want to increase the output current by increasing AE2 by 10 times. Recalculate MR = Io/IREF, Io, VBE1 and VCE1 if AE1 = 2,AE2 = 20. Does the output current increase 10 times compared to (a)? Marks) (c) What is the maximum mirror ratio attainable by increasing AE2 ? (10 Marks) Figure 1 2. Now, draw the AC small signal model for this same circuit in Figure 1 and find an algebraic expression for the input resistance, Rin, including the effect of V. 1. Evaluate the value of Rin using the parameters given in part 1(a) and considering VA = 100 V−1. (40 Marks)

Consider a pseudo-NMOS gate shown in the figure, VDD = 3.3 V and all the transistors are sized 1/1. Find (1) the logic function implemented, (2) VOH and VOL, and (3) tpHL and tpLH if the capacitance at the output note is 50 fF. tpHL is the time required for Vo to change from VOH to 0.5 VDD and the tpLH is the time required for VO to change from VOL to 0.5 VDD The technological parameters are μnCox = 4 μpCox = 160 μA/V2, |γ| = 0.5 V1 /2, 2ϕf = 0.5 V, λ = 0.001 V−1, Vtno = 0.6 V, and Vtpo = −0.8 V.

Consider the current mirror depicted in Fig. 2 where Iin = 100 μA, R = 2 kΩ, and each transistor has W/L = 10 μm/0.4 μm. Given the 0.35 μm CMOS device parameters in Table 1.5 , what drain voltage at Q2 will ensure that Iin is precisely equal to Iout?

Assuming (W/L)1 = 2 μm/0.18 μm and (W/L)1 = 5 μm/0.18 μm, find the voltage transfer characteristic of the inverter in Fig. 1. Compute the voltage expressions for every operating region of the transistors and find the drain currents of M1 and M2 for Vin = VDD/2. Comment on possible improvements to reduce this current. Figure 1 For the transistors in this question, assume VDD = 1.8 V, μnCox = 100 μAV−1, μpCox = 50 μAV−1, Vthn = 0.4 V, Vthp = −0.5 V, λn = λp = 0.

For all circuits, do not consider channel length modulation for calculating bias points. Unless otherwise specified, channel length modulation effect needs to be considered for small-signal analysis. All answers should be given to the second decimal place. Circuit and device parameters are: Vdd = 5 V;VTn = VTp = 1 V; μnCox = 50 μA/V2; μpCox = 25 μA/V2; λn = λp = 0.01 V−1; Lmin = 1 μm Figure 1 (for problems 1-3) Figure 2 (for problems 5-9) Figure 1: Transistor M1 has (W/L) = (160 μm/2 μm) and a bias current Iout = 2 mA. We desire M1 to be in saturation. You should assume λn = 0 for problems (1)-(3). Determine the ratio R1 /R2 required. 1 point Let VTn increase by 10% to 1.1 V. What is the new value of Iout in mA ? 1 point Let μnCox increase by 10% to 55 μA/V2. What is the new value of Iout in mA ? 1 point Figure 2: The circuit has Iref = 2 mA and Vp = 4 V. Transistors M1, M2 and M3 have (W/L) = (80 μm/1 μm). Determine the value of vx. (in volts) 1 point Determine the minimum allowable value of Vb (in volts) such that all devices are in saturation. 1 point Determine the maximum allowable value of Vb (in volts) such that all devices are in saturation. 1 point Determine Vb (in volts) such that vX = VY. 1 point determine the output resistance of this circuit ∂Vp/∂Iout in MΩ. 1 point Description for questions 9-10: An NMOS device with ID = 1 mA must operate in saturation with drain-source voltages as low as 0.5 V. The minimum required small-signal output impedance is 400 kQ. {Hint: You need to use the relations: rout = 1 /(λ⋅ID); λ⋅L = constant; and expression for VDS, sat = VGS−VT} Determine the length of the device in μm. 1 point Determine the width of the device in μm. 1 point

The following circuit applies to Questions 11 through 13. Given: μnCox(W/L)1 = 10 mA/V2, μpCox(W/L)2 = 20 mA/V2, Vtn = |Vtp| = 0.4 V, R = 5 kΩ, and VDD = 1.5 V Assuming that both MOSFETs M1 and M2 are biased in saturation, and that λ = 0, find the value of ID1 (in mA ) so that the small-signal gain, vout /vin , of this amplifier is −10 V/V

(a) For the circuit shown in figure 1(a), find the following [20] i. Vi(s)/Vs(s) ii. Vo(s)/Vi(s) iii. Vo(s)/Vs(s) iv. Draw the magnitude plot for |T(jω)| in dBvs. frequency v. Lower 3 dB cut-off frequency fL vi. Upper 3 dB cut-off frequency fH vii. Bandwidth (b) Consider the n-channel MOSFET amplifier in figure 1(b). ID = 12 kn′W L(VGS − Vt)2, VDD = 5 V, RL = 2 kΩ, kn′WL = 1 mA/V2, Vt = 1 V. You can ignore channel length modulation. CC is the input coupling capacitor. You can assume it is infinitely large. [10] i. Determine the required ratio RA/RB such that the MOSFET gm = 1 mA/V. Remember that gm is defined as ∂ID/∂VGS ii. Draw the small-signal π model for the amplifier iii. Calculate the gain Vout/Vin (for gm = 1 mA/V ) (a) Figure for question 1 (a) (b) Figure for question 1 (b)

Q3. Consider the circuit of Fig. 4. Ignore the body bias effect (Perform intuitive analysis) Given: MOSFET: λ = 0.1 V−1, Vtn = 1 V, μnCox = 100 μA/V2, Vov = 0.2 V BJT: VBEon = 0.6 V, VA = 100 V and VCEsat = 0.2 V I. Identify the topology of stage 1 and stage 2. II. Calculate the current ID1 . III. Calculate the voltage swing at nodes Vx and Vout . IV. Sketch and label the small signal model. V. Calculate the Gm and Rout of Stage-1. Hence, find the gain Vx/Vin and Vout /Vx. (Hint: Consider loading effect of stage 2 in calculations) VI. Assume, node Vx is connected to node B. Now, calculate Gm and Rout of first stage (Hint: Consider loading effect of stage 2 in calculations) [25 Marks]

An amplifier is designed so that it amplifies a differential input signal by a factor of 100 and it attenuates a common-mode signal by a factor of 10 . What is the CMRR of the amplifer in dB ? 80 dB 60 dB 40 dB

For a differential amplifier shown below, we may define CMRR OA as the common-mode rejection ratio of the op-amp itself, and CMRRR = 12(2 R2 R4+R2 R3+R1 R4 R1 R4−R2 R3) as a kind of CMRR to account for the resistance variations. Then it can be shown that the CMRR of the differential amplifier circuit, CMRR0 is given as CMRRD = CMRRRCMRROA+1 /4 CMRRR+CMRROA When CMRRRCMRROA≫1 /4, then a useful relationship is 1 CMRRD≈1 CMRRR+1 CMRROA (a) Show that when R2 = R4 and R1 = R3 then CMRRR→∞, and CMRRD = CMRROA. (b) Now assume that R2≈R4 and R1≈R3. Given that resistors have tolerances |δRR| < t, show that the worst-case CMRRR is CMRRR≈GD+14 t, where GD is the differential gain of the circuit. (c) For a 0.1% tolerance on resistance values, and a gain of 100 , compute the worst-case CMRRD when CMRROA is 100 dB. How about when the resistor tolerances are only 1% ? (d) Show that if R4 is replaced by a potentiometer (a variable resistor) then CMRRD may be optimized

For the cascaded current amplifier shown below, the parameters are: Rs = 20 kΩ, Ro1 = Ro2 = Ro3 = 4.7 kΩ, Ri1 = Ri2 = Ri3 = RL = 100 kΩ, and Ais1 = Ais2 = Ais3 = 100. Find (a) the effective current gain Ai = io/is, (b) the overall voltage gain Av = vo/vs, and (c) the power gain Ap = PL/Pi. Give the answers in dB unit.

Problem 1 : The differential amplifier in the following figure utilizes a resistor Rss to establish a 1−mA dc bias current. Note that this amplifier uses a single 5−V supply and thus the dc common-mode voltage VCM cannot be zero. Transistor Q1 and Q2 have kn′W/L = 2.5 mA/V2, Vt = 0.7 V, and λ = 0. (a) Find the required value of VCM. (b) Find the value of RD that results in a differential gain Ad of 8 V/V. (c) Determine the dc voltage at the drains. (d) Design the single-ended-output common-mode gain ΔVD1/ΔVCM. (Hint: You need to take 1/gm into account. ) (e) Use the common-mode gain found in (d) to determine the change in VCM that results in Q1 and Q2 entering the triode region.

Q2 Suppose the MOSFET in a Boost converter with the following specification is driven with the vGS voltage shown and vDRV = 8 V. Assume the filter inductor and capacitor are designed so that the output voltage and inductor current can be seen as constants. (a) Estimate the Gate driver loss, assuming the diagram of the required gate charge for the MOSFET is as show: (b) Estimate the VDSIDS power loss if the time required for switching are: tri = 30 ns, tfv = 20 ns, trv = 25 ns, tfi = 15 ns. on transient off transient Hint: Find IIN by assuming PO = PIN

For the differential amplifier shown below, assume V+ = 12 V, V− = −12 V, R1 = 11.5 kohms, Rc = 4.7 kohms, and VA = 100 V. What is the CMRR if the circuit has a single-ended output (i. e., vo = vc2)? Enter your answer in dB, rounded to the closest integer value.

For the differential amplifier shown below, what is the value of the output resistance R out if Rc = 30 kohms and the output is taken differentially (i. e. , vo = vc1 vc2)? Assume VA = 100 V. Rout = 26 kohms Rout = 30 kohms Rout = 46 kohms Rout = 60 kohms

For the differential amplifier shown below, assume IQ to be a current source with output resistance Rout = 100 kohms. Ignoring mismatches, what is the common-mode gain of the circuit if the output is taken differentially (i. e. , vo = vc1 - vc2)? Assume Rc = 20 kohms. Acm = 0 Acm = 0.008 Acm = 0.02

Q2 - For the amplifier circuit in Figure Q2, VDD = 6 V, IB = 1 mA, RG1 = RG2 = 2 MΩ, RL = 10 kΩ, and CA = C2 = 0.1 μF. The transistor is characterized by the following parameters. Vs = 0.5 V, kn = 2 mA/V2, and VA = 20 V Figure Q2. (a) Find Vov and VGs for the transistor. Ignore channel length modulation for this part. (b) What is the midband gain of the amplifier? (c) What is the input impedance (Rm) of the amplifier? (d) What is the output impedance (Ro) of the amplifier? (e) Find the lower −3 dB cutoff frequency (fL). (f) Construct the small signal equivalent circuit in Ltspice and run an AC simulation. Mark the lower -3 dB(f1) frequency. Compare it to your hand calculation.

Assume 2|ϕFP| = 0.8 V. The following figure shows the relationship between threshold-voltage (VTH) and body voltage (VB) of a NMOS. The source voltage is 0 V(VS = 0 V). What is the body effect coefficient (γ)?

(a) Simulate the circuit in LTSpice and find ID and VO as functions of VGG in the range VGG ∈ [0; 5.0 V]. Use the MOSFET model from Brightspace - see instructions in Part 4. VGG is now set to 3.0 V. (b) Calculate ID and VO "by hand" by using relevant data from the ZVN3306 A datasheet. Compare with results from simulation in (a). VGG is now changed to a pulse train with frequency of f0 and a duty cycle of 50% (c) Calculate an estimate of the maximum value of f0 in order to maintain proper switching of the output voltage. Base the estimate on relevant information from the ZVN3306 A datasheet. (d) Calculate the peak gate current IG. Set the frequency of the pulse (f0) to 1 kHz Figure 2.1 N-channel MOSFET circuit for part 2.

Assuming full symmetry in the differential amplifier shown in Figure 5, Find the differential gain expression. (Take λ ≠ 0. )

Circuit diagrams of six different single-stage common-source amplifiers. In the circuits Vdd = 5 V, (W/L)1 = 100, (W/L)2 = 25, Vb = 2 V, RD = 500 Ω, RS = 100 Ω, Vin = 3 + 0.01sin⁡(2000πt + 90∘)V. (a) Find out the bias points (DC node voltages and branch currents) of the circuits. If any of the transistors are not in the expected region of operation, modify the circuits by changing the aspect ratios of the transistors for the proper functionality. (b) Calculate the small signal gain, input resistance, and output resistance of the circuits. (c) Plot Vin and Vout for 3 ms and neatly label it. (d) Calculate Vout , max and Vout , min , and hence the maximum output voltage swing of the amplifiers. Using this find out what is maximum allowable input voltage swing. By changing the aspect ratios of the transistors, can you obtain the maximum possible voltage swing? (e) Can you increase the gain of the amplifiers by a factor of 2 just by changing the aspect ratios of the transistors? (f) Repeat (a)-(e) assuming the second order effects are present in the transistors.

You are required to design an all-NMOS differential amplifier with a single sided output in a 0.35 um CMOS process. You have a single 3.3 V DC supply rail at your disposal. Your amplifier should make use of an active load amplifier configuration. Use the following NMOS device in your SPICE simulation: . MODEL MYNFET1 NMOS VTO = 0.6 KP = 170 E−6 W = 0.35 E−6 L = 0.35 E−6 Structure your report to match the grading rubric below. Question 1 Using an ideal current source with 2 MΩ output impedance, design the DA for 15 V/V differential gain over a 20 kΩ load resistor connected in a single sided output configuration. [3] Present appropriate design calculations for RD, IQ and the device W/L

Now, consider the high-swing cascode current mirror shown in Figure 3 below. Figure 3. High-swing NMOS cascode current mirror for Problem 3. a) By hand, determine Mx2 length Lx2 such that VDS2 is 25% larger than VON2; i. e. , design Lx⁡2 such that VDS2 = (1+α)VON2 = 1.25VON2, with α = 0.25. b) By hand, determine Vout, min such that M2 and M4 are in saturation. Assume Lx2 and VDS2 as in part (a). c) By hand, determine the small signal output resistance. Assume M2 and M4 in saturation.

The circuit in the figure below has a PMOS transistor with parameters kn = 120×10−6 V/A2, VT = 0.9 V, W/L = 7 μm/0.5 μm. Channel length modulation is neglected. Simulation model of the PMOS device is given at the end of the question. a. Calculate the values of Vout for Vin values varying from 5 V to 0 V (with steps of 1 V). Note the operating region of the PMOS device in each step.

Consider a BJT differential amplifier biased with a Widlar current source, as shown in Figure 4. The transistor parameters are: β = 200, VBE(ON) = 0.7 V (except for Q3 and Q4), VA = ∞ for Q1 and Q2, and VA = 100 V for Q3 and Q4. Reverse saturation current, Is for transistor Q3 and Q4 is given as 1×10−15 A. From analysis, it is determined that I1 = 0.5 mA, la = 400 μA, v1 = v2 = 0 V, VCE2 = 2.7 V and CMRR (dB) = 80 dB Figure 4 a) Calculate the value of resistors R1, R2 and RC. b) Find the amplifier's differential-mode voltage gain (Ad), common-mode voltage gain (ACM) and common-mode output resistance ( Ricm ). [Ricm ≈ (1+β)Rocs where Rocs is the output resistance of the current source ] c) Draw the pnp version for the differential amplifier of Figure 4. Clearly label all resistors and currents.

Next, consider the simple cascode current mirror shown in Figure 2 below. a) Explain the purpose of diode-connected devices M1 and M3. b) By hand, determine Vout, min such that both M2 and M4 are in saturation. How does this compare to Problem 1, part (a)? c) By hand, determine the small signal output resistance Rout. Assume M2 and M4 in saturation. Figure 2. Simple NMOS cascode current mirror for Problem 2.

Question 1 (Differential amplifiers) (20) The transistors of the differential pair of Figure 1 are supposed to be matched. Assume that for both transistors VBE = 0.7 V and β = 100. The two transistors are biased for Vin1 = Vin2 = 0 V. Find gm1, gm2, rπ1 and rπ2. (4) For vin1 = vid/2 and vin2 = −vid/2, where vid is a small signal differential input, find the magnitude of the differential gain ∣(vo1− Vo2)/vid if the output is taken differentially. (4) Find the differential mode input impedance Rid. (4) For vin1 = vin2 = vicm, find the common mode input resistance Ricm. (4) Find the magnitude of the single ended common mode gain |vol/vicm | and calculate the single-ended Common Mode Rejection Ratio CMRR if the resistance connected to the collector of Q2 has an error of ±1%. (4) Figure 1

Consider the simple current mirror shown in Figure 1 below. Figure 1. Simple NMOS current mirror for Problem 1. a) By hand, determine Vout, min such that M2 is in saturation. b) By hand, determine the small signal output resistance Rout. Assume M2 in saturation. c) Sketch Iout vs. Vout over the range Vout, min = Vout ≤ VDD . d) In SPICE, verify your result of part (a), and briefly discuss any agreement/disagreement between the hand analysis and simulation results. e) In SPICE, verify your result of part (b), and briefly discuss any agreement/disagreement between the hand analysis and simulation results.

Verify the operations of current mirror circuit by LTSpice simulation. 5.1 (5 point) Create the following MOSFET current mirrow schematic, assigning the parameters and label the X and Y nodes (Hints: For M1, you need to "mirror" NMOS4). For M1 and M2: kn = 200 u vT0 = 0.5 W1 = W2 = 50 u L1 = L2 = 10 u IREF = 50 uA VDD = 5 V

The two cascaded voltage amplifiers in the left circuit below are coupled using a coupling capacitor and the equivalent circuit is shown on the right. Find the value of the coupling capacitor C in μF to give a 3 dB lower cut-off frequency of 88 Hz. Give your answer to 3 decimal places.

Q1. i) (12%) The schematic below shows a typical NAND2 gate whose inputs are A and B. First, size the transistors with reference to a unit inverter, and arrange the inputs if we know A arrives later than B. ii) ( 8% ) Now, because we know the input signal order, we can make the fall time even faster by down-sizing the NMOS associated with input A while keeping the overall pull-down equivalent resistance to be the same as before. Suppose the NMOS for A is sized to be 4/3, what should be the size of the NMOS for B? iii) (20%) Following from (ii), what are the logical efforts for inputs A and B, respectively? What is their average value and how does it compare to the logical effort of a typical NAND2 as in (i)? iv) (10%) When we do not really know the input order, is there any advantage from the gate below compared to that in (i)?

Q2. (50%) From the study of logical effort we learned the fastest circuit is achieved whenever the stage effort is around 4. The following circuit is designed with this in mind by making the stage effort gihi on the lowest critical path all 4. Note there is a compound gate AOI22 in the 2 nd stage. In each gate, the total capacitance seen by one pin is denoted P#N# where the hash signs denote the PMOS and NMOS sizes, respectively, and are all integer values. Fill in all the missing P#N#. Then, compute the normalized delay through the network.

For the gate shown in the Figure (a) calculate the internal capacitances at nodes X and Y. (b) calculate the propagation delay tpLH in the case when the input A changes from Vdd to 0 (step input) and the other inputs are B = Vdd and C = 0. (c) calculate the propagation delay tpHL in the case when the input A changes from 0 to Vdd (step input) and the other inputs are B = Vdd and C = 0. In the calculation of the delays you should consider the effect of internal capacitances. Use the following parameters: Vtn = 0.4 V, Vtp = −0.4 V, VDD = 2.5 V. All transistors have minimum length L = 0.25 μm. Assume W = 0.5 μm. Use the following values for the transistor capacitances: Cd = 1 fF/μm. Use the following values for the transistor resistances: Rsq,n = 13 kΩ and : Rsq.p = 31 kΩ.

Calculate the values of AV, Rin, and ROut for the amplifier in the following figure if RI = 5 kΩ, RG = 10 MΩ, R3 = 36 kΩ, RD = 1.8 kΩ, and VDD = 16 V. Use Kn = 400 μA/V2, λ = 0.02 V−1, and VTN = −5 V. Use SPICE to verify the results of your hand calculations. Assume f = 3,000 Hz, C1 = 2.2 μF, and C2 = 10 μF. (Round the final answer to two decimal places and Include a minus sign if necessary. ) AV = MΩ Rin = kΩ Rout = Using SPICE, AV = , Rin = MΩ, and Rout = kΩ.

CD-CS Multistage Amplifier CS-CS Multistage Amplifier Q3. One of the techniques to improve the bandwidth of the common-source (CS) amplifier is using a common drain (CD) amplifier before the CS amplifier stage. You want to compare the performance of CD-CS configuration with a CS-CS amplifier configuration in terms of gain and bandwidth. Let all the transistors be identical and at the same biasing current. Let gm = 1.25 mS, RL = 100 KΩ, Cgd = 12π fF a) Find the gain for each circuit. b) Find the poles caused by Cgd shown in each circuit.

Question 1 Given the following amplifier circuit with a signal source consisting of internal resistance Rs = 200 kΩ and the amplifier having an input resistor Ri = 15 kΩ, the open loop gain of 950 V/V, and the output resistor Ro = 1.5 kΩ. The output of the amplifier is connected to a load RL = 100 Ω. a) What is the overall voltage gain when measuring between the source internal voltage and the load? b) What is the overall gain if we remove the amplifier to connect the load to the source directly? c) Give your comments on the efficiency of the amplifier circuit. What is the optimal design of the amplifier circuit and explain the reason?

Question 10. The pMOSFET circuit below has VDD = −8 V, Vt = −1 V, k = 0.75 mA/V2 and λ = 0. Specify suitable resistance values to bias the device at ID = 1.5 mA with VD halfway between the values corresponding to the edge of conduction (EOC) and the edge of saturation (EOS). Specify R1 and R2 in the mega-ohm range. ( 1 Point)

Consider the circuit in figure. The bias current in the circuit is 0.3 mA and the transistors are biased such that, |Vovn| = 0.5∗|Vovp| = 150 mV. The technology parameters are given by VDD = 1.8 V, |VAp| = 2|VAn| = 12 V. Fill in the table with proper units. Neglect channel length modulation for biasing calculations. (2+4+4+2) Effective small-signal transconductance of the amplifier Small-signal input resistance of the amplifier Small-signal output resistance of the amplifier Small-signal open circuit voltage gain

Transistors' Parameters Kn1 = Kn2 = Kn4 = 1 mA/V2; Kn3 = 2 mA/V2 VTn = 1 V (for all) λ1 = λ2 = λ4 = 0, λ3 = 0.01 V−1 Circuit Parameters VDD = 12 VRD1 = RD2 = 4 K Circuit Parameters i) Determine RF to set Iref to 1 mA. ii) Determine the DC values and states of the transistors. iii) Determine Acm, Adm and CMRR.

For the MOSFET current source of Fig. Q1(b), the circuit values are VDD = +12 Volts, VSS = 0, and IREF = 100 μA. The transistors are matched and their parameters are VT = 1.8 Volts, kn = 250 μA/V2 and λ = 0.01 V−1. Calculate ILOAD for (i) VDS2 = 2.5 Volts, (ii) VDS2 = 4 Volts and (iii) VDS2 = 10 Volts. Calculate the value of for which transistor T2 enters the linear region and hence determine the range of RLOAD values that can be used for this current source. Fig. Q1(b)

Required information A resistive load inverter in two logic states is given as follows: Let VTN = 0.6 V. For the circuit shown in the figure, VL = 0.5 V, VH = 2.6 V, VDD = 2.6 V, Kn′ = 100 μA/V2, VDS = 0.5, VTN = 0.6 V and power P = 0.0001 W. Find the new values of R and (W/L)S assuming that the power dissipation remains the same?

Required information The outputs of two CMOS inverters are accidentally tied together, as shown in the given figure: What is the voltage at the common output node if the NMOS and PMOS transistors have W/L ratios of 20/1 and 40/1, respectively and if Kn = 2000 μA/V2, and Kp = 1600 μA/V2 ? VDSN = V (Round off the solution to three decimal places. ) VDSP = V (Round off the solution to two decimal places.)

Consider the low swing driver of Figure 1 , and assume that Vn0 = 0.4 V, Vtp0 = −0.5 V. a. What is the voltage swing on the output node (Vout ) ? Assume y = 0. b. Estimate (i) the energy drawn from the supply and (ii) energy dissipated for a 0 V to 2.5 V transition at the input. Assume that the rise and fall times at the input are 0 . Repeat the analysis for a 2.5 V to 0 V transition at the input. c. Compute tpLH (i. e. the time to transition from VOL to (VOH+VOL)/2). Assume the input rise time to be 0. VOL is the output voltage with the input at 0 V and VOH is the output voltage with the input at 2.5 V. Assume that Kn′ = 100 uA/V2. d. Compute VOH taking into account body effect. Assume Y = 0.4 V1 /2 and 2φF = 0.6 V for both NMOS and PMOS. Figure 1 - Low Swing Driver

The inverter below operates with VDD = 0.4 V and is composed of |Vt| = 0.6 V devices. The devices have identical I0 and n. Assume n = 1.5. a. Calculate the switching threshold (VM) of this inverter. b. Calculate VIL and VIH of the inverter. c. Calculate noise margin (NML and NMH) of this inverter. Figure 2 - Inverter in Weak Inversion Regime

You have to fabricate a CMOS inverter in the latest 3-nm technology (L = 3 nm), for which VDD = 1.3 V, Vtn = |Vtp| = 0.4 V, (W/L)n = 5, and kn′ = 4.2kp′ = 450 mA/V2. a) Find the Noise Margins and total area for the following conditions: i. Match case (kn = kp) ii. Wp = 2.1Wn b) Which condition would you choose between the two previous and explain why? c) Find the dynamic power if you know that the total equivalent capacitance at the output will be C = 15 fF and you are required to operate the inverter at f = 2.6 GHz. d) For the case when (W/L)p = 2.1(W/L)n, find the propagation times ( tPHL, tPLH and tp). Assume again C = 15 fF.