For the differential amplifier given, we have a gm mismatch for the two transistors. Suppose that the gm1 and gm2 are given as below: gm1 = gm + 12 Δgm gm2 = gm − 12 Δgm State what is the effect of this mismatch in common-mode gain and in CMRR for both single-ended and differential input. To increase the CMRR(differential output) what would you chose to double the RSS or to halve the mismatch Δgm.
Q2. Consider the differential amplifier where the load is a capacitor Co and the output voltage is taken differentially across Co. Let gm = 1.25 mS, RD = 1 KΩ, RSS = 1 MΩ, Co = 12π nF You are asked to: a) Draw the half circuit for the differential mode. b) Find the bandwidth of the differential mode in Hz. c) Draw the half circuit for the common mode. d) Find the bandwidth the common mode in Hz.
For the below differential amplifier assume β = 100, VA, npn = 120 V, VA, pnp = 80 V. The Current source provides 1 uA_ of current for Q1 and Q2 not 1 mA. (a) Find the value of the current source I, if the voltage across R1 and R2 is 80 mV. (b) Calculate the small signal differential gain (Adm) for C = 0 and C = 10 pF.
The differential amplifier above has the following parameters: βo = 150, VCC = 5 V, VEE = 5 V, VBE−on = 0.7 V, REE = 20 kΩ, R1 = 3 kΩ, and RC = 20 kΩ. v1 and v2 are purely AC signals with 0 DC voltage. Determine the following: (a) The DC Q-points for Q1 and Q2. [4 pt. (b) Draw the differential-mode and common-mode AC equivalent half-circuits for the differential amplifier. [ 6 pt. ] (c) What is the differential-mode gain (Add) ? [4 pt. ] (d) What is the common-mode gain (Acm)? [4 pt.] (e) What is the CMRR? [4 pt.] (f) What is the differential-mode input resistance? [4 pt.] (g) What is the common-mode input resistance? [4 pt.]
For the circuit as shown below, all the BJTs Q1, Q2, Q3 and Q4 are identical, VBE = 0.7 V, β = 80, VA = 100 V, neglect rx and ro1,2 a) What are the DC collector current IC and DC collector voltage VC of Q1 and Q2 ? You may consider IC3, 4 = IE3, 4 in this step ( 6 marks) b) What is the input common-mode range for this differential amplifier? (10 marks) c) Determine the differential voltage gain Ad(8 marks) d) Determine the differential input impedance Rid and output impedance Rod, include RC ( 14 marks) e) If the β of Q2 is equal to 90 due to fabrication tolerance and the other components are perfect, what are the resulting common mode gain Acm and CMRR? (12 marks)
Q.6. a) Draw the differential small-signal half-circuit for the circuit shown in Figure 2.2. Clearly show the input, output, grounds and label all resistors. [3 marks] b) Draw the transfer characteristics ( vcovsic ) of Q1 and Q2. [2 marks] c) For the circuit shown in Figure 2.3, assume that β = 100. Calculate the voltage gain and the input resistance. [6 marks] [11 marks] Figure 2.2: Circuit for Q6 a/b Figure 2.3: Circuit for Q6 c
Consider the differential amplifier shown in Fig. 8. For both transistors, β = 100, VT = 26 mV and VA = 100 V. (a) Draw the differential mode half circuit and determine the differential gain (numerical answer needed). (b) Assume that, during manufacturing, a small mismatch appears where the collector resistance connected to Q2 has increased by 2%. Determine the common mode (to differential mode) gain (numerical answer needed). (c) Determine the CMRR (numerical answer needed). Propose two design strategies to improve the CMRR considering this resistor mismatch and circuit topology. Fig. 8.
Question-3: Sketch the voltage transfer characteristic of the NMOS inverter circuit given in Figure 3 by calculating the output voltage Vout for Vin = 0, 2, 4, and 5 V. Find also noise margins. (K = 1 mA/V2, Vt = 1 V for the NMOS transistor. ) Figure 3: NMOS inverter
Q 1: Assume μnCox = 200 μA/V2, (WL)M1, M2 = (10 μm/1 μm), Vthn = 0.4 V, λ = 0 For the figures given below (upper part of circuit is not shown), Vin1 = VCM + (vid/2) and Vin2 = VCM − (vid/2). If −0.36 V ≤ vid ≤ 0.36 V, what is the bias current provided by M3 ? If Vb = 0.64 V, what is the size of M3 ? If vid, max is applied at gate of M1 with gate of M2 grounded, what is the voltage Vp ?
Q2. The differential amplifier shown below has mismatched collector resistors. Calculate differential mode and common mode double ended voltage gain and the common-mode rejection ratio (CMRR) of the amplifier if the output is the differential output voltage v0. Q1≡Q2 β = 100 VBE(ON) = 0.7 VR = 100 kΩ ΔR R = 0.01
For the given differential amplifier with current mirror load, assume: L = 1 μm, Bias Current (ISS) = 0.5 mA, Overdrive Voltage (Vov) = 200 mV, λN = 0.1 V−1, λP = 0.05 V−1, Vthn = 0.4 V, Vthp = −0.4 V, μnCox = 250 μAV2, μpCox = 50 μA/V2 Determine transconductance (gm) for every MOS transistor. Determine output impedance (rds) for every MOS transistor. Calculate the theoretical value of differential gain (Av) using formula. Simulate the differential amplifier with proper design considerations on LTSpice simulation platform and compare the simulated gain with the calculated gain. NOTE: Clearly mention the assumptions taken while solving the problem. For simulation, determine W/L values for each transistor using formulas. Take snapshots of the waveforms and schematic in LTSpice software and include these in your response document. The instructions to
Consider the two inverter circuit below. V01 is the output voltage of inverter 11, V12 is the input voltage of inverter 12. Both inverters have the following characteristics: VDD = 5 V, VIL = 0.8 V, VIH = 2.0 V, VOL = 0.33 V, and VOH = 4.3 V (8 pts) a. Calculate the inverter noise margins. b. Can the circuit tolerate 1.5 V of noise between VO1 and V12 ? (discuss your answer)
Common-source topology. Determine the voltage gain of the circuits shown below assuming λ ≠ 0. (a) (b) Calculate the voltage gain AV and output impedance Rout of the common-source with source degeneration topology assuming λ ≠ 0.
Part 2: Set Up Basic Differential Amplifier at the O-Point 3. Design - Design the basic differential amplifier shown on the right using 2N2222 transistors for Q1 and Q2, such that VC1 = VC2 = 10 V when the inputs are both shorted to ground. Calculate the value of the one-sided output differential mode gain Ad for the circuit you now have. This is the level of small signal gain you should expect experimentally. The AC amplitude of the output voltage Vo (oscillating around 10 VDC) will be Ad times the amplitude of the input differential voltage (Vd = V1−V2). You will have to make sure that, when Vo oscillates, it does not exceed the V+ − V2 range.
TYU 9.11 All parameters associated with the instrumentation amplifier in Fig-ure 9.26 are as given in Exercise Ex 9.8, except that resistor R2 associated with the A1 op-amp is R2 = 50 kΩ±5%. (a) Determine the maximum and minimum possible values of the common-mode gain. (b) Determine the maximum and minimum possible values of the differential-mode gain. (c) Determine the minimum CMRR(dB). (Ans. (a) Acm = 0; (b) Ad(min) = 5.87, Ad(max) = 156.75; (c) CMRR = ∞) Figure 9.26 Instrumentation amplifier
For all circuits, do not consider channel length modulation for calculating bias points. Unless otherwise specified, channel length modulation effect needs to be considered for small-signal analysis. All answers should be given to the second decimal place. Circuit and device parameters are: Vdd = 5 V; VTnn = VTp = 1 V; μnCox = 50 μA/V2; μpCox = 25 μA/V2; λn = λp = 0.01 V−1; Lmin = 1 μm Figure 1 (for problems 1-3) Figure 2 (for problems 5-9) Figure 1: Transistor M1 has (W/L) = (160 μm/2 μm) and a bias current Iout = 2 mA. We desire M1 to be in saturation. You should assume λn = 0 for problems (1)-(3). Determine the ratio R1 /R2 required. 1 point Let VTn increase by 10% to 1.1 V. What is the new value of Iout in mA ? 1 point Let μnCox increase by 10% to 55 μA/V2. What is the new value of Iout in mA ? 1 point Figure 2: The circuit has Iref = 2 mA and VP = 4 V. Transistors M1, M2 and M3 have (W/L) = (80 μm/1 μm). Determine the value of vx. (in volts) 1 point Determine the minimum allowable value of Vb (in volts) such that all devices are in saturation. 1 point Determine the maximum allowable value of Vb (in volts) such that all devices are in saturation. 1 point Determine Vb (in volts) such that VX = VY. 1 point determine the output resistance of this circuit ∂Vp/Iout in MQ. 1 point Description for questions 9-10: An NMOS device with ID = 1 mA must operate in saturation with drain-source voltages as low as 0.5 V. The minimum required small-signal output impedance is 400 kΩ. {Hint: You need to use the relations: rout = 1 /(λ⋅ID); λ⋅L = constant; and expression for VDS, sat = VGS−VT }Determine the length of the device in μm. 1 point Determine the width of the device in μm. 1 point
Q1) For the circuit given differential amplifier, a) Draw differential mode half circuit, b) Determine differential mode gain, Adf = vo1−vo2 vi1−vi2. c) Find differential mode half circuit input and output resistances d) Find differential mode input and output resistances. e) Draw common mode half circuit. f) Determine common mode gains, ACM,half = vo1 vCM and ACM = vo1−vo2 vCM g) Find common mode half circuit input and output resistances h) Find common mode input and output resistances.
Q1. Consider the idea amplifier shown with voltage gain = −G, Zin → ∞ and Zo → 1000 a) Find the poles of the circuit and the cutoff frequency in Hz if, R1 = R2 = R3 = 1 kΩC1 = C2 = 12π nF b) The total gain in this circuit is G2, if we add more stages such that the total gain stays the same but we want to bandwidth to improve by a factor of 10 . What will be the gain of a single stage consider that the total number of stages is now 10 . Show your equations.
Using the half-circuit analysis, find the differential voltage gain for the circuit (All differential pairs are symmetrical, λ > 0 )
Suppose you have designed the circuit above with Ra = Rc = 100 Ω, and chosen Rb and Rd such that Vout = Adm(Vb − Va), where, Adm is the difference-mode gain, and the common mode gain is zero (i. e. CMRR is infinity). However, the resistors you've used to build the circuit are not precise. Each of them has an x% error (therefore, a resistor with a nominal value of 100 ohms will actually have a resistance of 99 or 101 ohms). Write a Matlab program to find the worst possible CMRR for a given value of x and Adm. Plot the CMRR (in dB) vs. x for x = 1, 2, …10. Obtain three graphs (and display in the same window) for Adm = 1, 10, 100.
9.20 Find the differential half-circuit for the differential amplifier shown in Fig. P9.20 and use it to derive an expression for the differential gain Ad ≡ vod/vid in terms of gm, RD, and Rs. Neglect the Early effect. What is the gain with Rs = 0 ? What is the value of Rs (in terms of 1/gm ) that reduces the gain to half this value? Figure P9.20
Find the differential half-circuit for the differential pair shown below and use it to derive an expression for the differential gain Ad≡vod/vid in terms of gm, RD and Rs. You may neglect ro (Early resistance of the MOSFETs) in derivation. What is the gain with Rs = 0 ? What is the value of Rs (in terms of 1/gm ) that reduces the differential gain to half of this value?
Problem5. The following MOS differential amplifier employs transistors with W/L = 100 and μnCox = 0.2 mA/V2. Please answer the following questions for the circuit shown above. a. Draw the differential-mode half circuit of the amplifier. b. Calculate the differential gain of the circuit. c. Draw the common-mode half circuit of the amplifier. d. Calculate the common-mode gain of the circuit if the drain resistances have 1% mismatch. e. Calculate the CMRR of the circuit in dB.
Assume all transistors are operating in saturation and λ = 0. (a) Sketch, in the same graph, ID1 and ID2 versus Vin1 − Vin 2 (b) For what value of Vin1 − Vin 2 are ID1 and ID2 equal? Show the point in the graph of part (a).
Assuming all of the transistors in the circuits are saturated and λ ≠ 0. (a) Draw the half circuit of differential amplifier (4 pts) and (b) find output impedance (4 pts). (c) Calculate the small-signal differential voltage gain (4 pts). (d) Calculate the small-signal common-mode voltage gain for differential output (4 pts). (e) Calculate the common-mode rejection ratio by using the results from (c) and (d) (4 pts).
a. [15 points] Calculate the small-signal differential voltage gain vout/(vin1 − vin2) in the circuit shown below. Assume perfect symmetry, but do not neglect channel length modulation. The N-channel MOSFET is characterized by (gm = X mA/V, ro = 75 kΩ), while the P-channel MOSFET is characterized by (gm = 0.8 mA/V, roP = 60 kΩ). The current sources have an output resistance of 120 kΩ ). Assume RSS = 4.2 kΩ. Hint: Use the half-circuit technique. X = 1.335 mA/V b. Repeat part (a) to find the [10 points] common-mode gain vout /vicm, and the [5 points] CMRR.
Draw the differential-mode half-circuit equivalent assuming the two current sources are ideal and both sides are fully identical and symmetrical. Derive an expression for the effective transconductance (Gm) of the circuit in (1) in the s-domain. What is the Gm at DC (ω = 0) ? Based on (2), calculate the zero and the pole frequency and sketch the effective transconductance (Gm) vs. ω. Assuming the output pole at 1 /RDCL is the dominant pole, determine the product of RSCS to achieve "pole-zero" cancellation. Based on this pole-zero cancellation determined in (4), sketch the gain response |Av| vs. ω, assuming ro = ∞.
Calculate the differential voltage gain ( =(Vout1 − Vout2)/(Vin1 − Vin2)) of the circuit below. Assume perfect symmetry and include channel length modulation. Use μnCox = 200 μA/V2, λn = 0.1, λp = 0.2 and ISS = 200 μA, ID5 = 50 μA, VGS−VTH = 0.1 V, VGS3−VTH = 0.2 V
For the differential amplifier shown, identify and sketch the differential half-circuit and the common-mode half-circuit. Find the differential gain, the differential input resistance, the common-mode gain assuming the resistances Rcc have 1% tolerance, and the common-mode input resistance. For the transistors, β = 100 and VA = 100 V. (Hint: Find IE, IC, gm, re, and ro ). Be sure to explain any assumptions (i. e. if you leave something out of a calculation, you need to explain why).
Problem3. Calculate the differential mode gain, common mode gain and CMRR of the differential amplifier shown above. Assume λ = 0 and neglect the body effect.
Question 4: Consider the differential pair in Figure below. All transistors are operate at Vov = 0.15 V:|Vt| = 0.25 V, μCox = 200 μA/V2, and VA = 10 V. VD = 0 at each M1 and M2 drain. a. Determine the value of RD and the (W/L) ratios of M1, M2, M3 and M4. b. What is the differential gain (Ad) of the circuit? c. What is the common mode gain (Acm) of the circuit?
SIM D∗9.57 The differential amplifier in Fig. P9.57 utilizes a resistor RSS to establish a 0.02−mA dc bias current. Note that this amplifier uses a single 2-V supply and thus the dc common-mode voltage VCM cannot be zero. Transistors Q1 and Q2 have kn′W/L = 1 mA/V2, Vt = 0.4 V, and λ = 0. (a) Find the required value of VCM. (b) Find the value of RD that results in a differential gain Ad of 15 V/V. (c) Determine the dc voltage at the drains. (d) Determine the single-ended-output common-mode gain ΔVD1/ΔVCM. (Hint) (e) Use the common-mode gain found in (d) to find the change in VCM that results in Q1 and Q2 entering the triode region. Figure P9.57
Figure 3. The input of the stage in Figure 3 is driven by voltage source Vsig with a relatively high impedance Rsig = 100 kOhm. Estimate the output resistance of the stage in Figure 3 in Ohm units. All BJT have the current gain of 80. All BJT dimensions are identical. The reference current is 100 uA. Your Answer:
In the op amp model above, open-loop gain A = 107 and VCC = 12 V. Suppose the inverting-input voltage is vn = 29 μV and the output voltage vO = 4 V. What is the noninverting input voltage vp (in micro-volts)?
Problem 2. Differential amplifier - current source load For the circuit in Fig. 2 (assume γ = 0), (b) Calculate minimum common-mode input, Vin, CM, if ISS requires at least 0.4 V across it. (c) For this value of Vin, CM , calculate maximum output voltage, Vout1,max and minimum output voltage Vout1,min that keeps transistors in saturation. Figure 2: Problem 2 NMOS: W = 10 μm, L = 0.5 μm, κn = 140 μA/V2, tox = 9 nm, μ0 = 350 cm2 /V/s, ϕ = 2ϕF = 0.9 V, Vt0 = 0.7 V, λ = 0.1 V−1( at L = 0.5 μm) and γ = 0.45(V). PMOS: W = 10 μm, L = 0.5 μm, κn = 40 μA/V2, tox = 9 nm, μ0 = 100 cm2 /V/s, ϕ = 2ϕF = 0.8 V, Vt0 = −0.8 V, λ = 0.2 V−1( at L = 0.5 μm) and γ = 0.4(V).
For the amplifier circuit below, given Kp = 4.6 mA/V2 assume λ = 0, Vtp = −1.4 V, Q−point (0.8 mA, 3.9 V), R5 = 10.5 Kohm Determine the maximum possible magnitude in V of output signal to keep the amplifier in the linear range.
Design a CMOS inverter circuit with the following parameters. The supply voltage is VDD = 1.3 V. The channel length of both transistors is Ln = Lp = 80 nm a) Determine the β ratio WP/Wn so that the switching (inversion) threshold voltage of the circuit is VM = 0.7 V b) The CMOS fabrication process used to manufacture this inverter allows a variation of the Vt, n value by ±20% around its nominal value, and a variation of the Vt, p value by ±20% around its nominal value. Assuming that all other parameters (such as μn, μp, Cox, Wn, Wp ) retain their nominal values, find the upper and lower limits of the switching threshold voltage (VM) of the circuit.
Estimate the delay through the circuit in Fig. Use the 180 nm process with 10/1 NMOS devices. Also verify the estimate with a SPICE simulation Solution: Do at your own. HINT: Use the quadratic dependence formula of the series connected transistors.
Problem 1. [100 pts] Biasing and small signal model of a basic differential amplifier with active load. Given the circuit below with the following conditions: Ideal voltage source VDD = 3.3 V, and ideal current source IB = 20 uA Input voltages: v2 = VCM + vd/2 v1 = VCM − vd/2 Differential input voltage: vd = v2 − v1 Common-mode input voltage: VCM = 2 VPMOS: Vt, p = −0.62 V, μpCox = 36 uA/V2, λp = 0.019[1 /V]NMOS: Vt, n = 0.48 V, μnCox = 90 uA/V2, λn = 0.025[1/V] All transistors have the length L = 2 um, except for M1 and M2 with L1 = L2 = 0.5 um. Width of the transistors: W6 = W7 = W = 4 um W5 = 2 W W3 = W4 = W W1 = W2 = 8 um. Assume all transistors in saturation.
Q. 3: Consider the schematic of an NMOS Wilson current mirror as shown in figure 3. Draw the pertinent ac equivalent circuit for the system. Figure 3 Given (for all transistors), K = μCox = 100 μA/V2, W/L = 10, VSS = −5 V, VTH = 0.5 V, VDD = 5 V, and VA = 20 V. Approximate analysis gives the output resistance of the mirror as Rout = gmr02. What should be the DC bias current Iout so that Rout becomes 100 Mega ohms?
The differential amplifier of Figure 2 uses BJTs with β = 100. Identify and sketch the differential and common-mode equivalent half circuits. Determine the differential and common-mode input resistances. Assuming the output is taken single-endedly (as shown), determine the differential and common-mode voltage gains and the CMRR. Figure 2
4 In Figure 3, a BJT differential amplifier input stage (Q1 & Q2) utilizing two 100 Ω emitter resistors drives a second differential amplifier stage (Q3&Q4). Stage 1 is biased with IT1 = 1 mA and stage is biased with IT2 = 2,5 mA. All BJTs have β = 150.4.1 Determine the signal differential voltage gain and input resistance of stage 1 , and the signal current gain from the input of stage 1 to the collectors of stage 2 i. e. |AI|≡ic3 ib1. 4.2 State two likely reasons for the addition of the emitter resistors to stage 1. Figure 3
5 The circuit diagram of a simple op-amp is shown in Figure 4. Figure 4 5.1 Perform an approximate dc analysis of the circuit to determine the dc currents and voltages everywhere in the circuit assuming the inputs are grounded, β > 1 and |VBE| ≈ 0,7 V. 5.2 Assuming the BJTs have β = 100, determine the differential voltage gain and input resistance, and the output resistance of the op-amp. 5.3 If due to production mismatch BJTQ has β = 120, determine the input bias current IB and input offset current IOS for this op-amp.
problem 1 Design the inverter (determine the W/L of each device) in Fig. 1 to have a self-bias voltage of 0.9 V and a quiescent current of 108 μA when self-biased. Ignore λ for operating point calculations. What is the dc gain of this inverter? (Use this inverter for the rest of the problems). For the following problems, use the data below: μnCox = 300 μA/V2, μpCox = 75 μA/V2, VTn = VTp = 0.6 V; λp = λn = 0.1 /V Problem 1 Figure 1: Circuit for
For an OPAMP with VDD = 3.3 V and input common-mode voltage (VCM) = VDD/2, the MOSFET model parameters are listed in page B-9 of Appendix B on Smith's CD. (1) As shown in Fig. 1, please calculate vo/vid(s) with its DC gain and pole locations, where vid = vin+ − vin−. (refer to Sections 8.5.3 and 9.7.2 in textbook). Then verify your results by PSpice with 0.5 μm CMOS model (in sedra_lib. lib). The sizes of all MOSFETs are listed below. (W/L)M1, M2 = 12 μm/0.5 μm (W/L)M5 = 2.5 μm/0.5 μm (W/L)M3, M4 = 5 μm/0.5 μm (W/L)M6 = 0.75 μm/0.5 μm
The current source shown in Fig. 2 is known as a "regulated cascode" circuit. Assume that both MOSFETs are biased in the saturation region so that the output current is set to IOUT. Find the dc currents IREF and IOUT in terms of VDD, VGS1, and VGS2. (Note that IREF ≠ IOUT for this circuit. )Find the output resistance of this current source in terms of the appropriate small-signal transistor parameters and resistor values. Figure 2
The circuit below is a two-stage amplifier with a common-source amplifier as the first stage and a source-follower as the second stage. Given parameters are like the following: R1 = 2 kΩ and R2 = 2 kΩ, and VDD = 6 V; and we assume two MOSFETs both operate in saturation and are characterized by parameters VT1 = 1 V, VT2 = 3 V, and K = 1 mA/V2. The threshold voltages of the first (left) and the second (right) NMOS transistors are VT1 and VT2, respectively, while they share the same K parameter. (Note: 3 sub-problems: 10 -points each sub-problem. ) (a) Find DC operating points (V1, VO1, VO2, ID1 and ID2) for achieving the maximum input signal amplitude. (Note: ID1 is a DC current flowing through the first stage and ID2 is a DC current flowing through the second stage). Show the whole process. Box all five answers.
Given the differential amplifier below. All transistors have the minimum gate length of 0.18 μm. The mobility of NMOS and PMOS are 0.065 m2/Vs and 0.025 m2/Vs. The threshold voltages are 0.6 V and −0.6 V. The supply voltage is 1.8 V. The Early voltages for NMOS and PMOS are 80 MV/m and 40 MV/m. The current IsS is set at 1 mA. a. Estimate the specific capacitance of the gate oxide (per m2). b. Add a circuit to generate the bias current Is5 from a reference current c. Which transistors could suffer bulk effect and draw the bulk connections. d. Choose a suitable value for the resistors. e. Choose a suitable bias voltage for the inputs. f. Choose suitable widths for the transistors. g. Derive an expression for the frequency-dependent (differential) gain of the circuit where you take into account the output load capacitance (CL on either side) and the parasitic capacitance parallel to and output resistance of the tail current source. h. Derive an expression for the frequency-dependent CMRR of your circuit taking into account the same parasitic capacitors and where you assume the transconductances from M1 and M2 are slightly different as well as the resistors RD1 and RD2. i. Derive an expression for the frequency-dependent PSRR of your circuit taking into account the same parasitic capacitors and where you assume the transconductances from M1 an M2 are slightly different as well as the resistors RD1 and RD2.
Find the width of all transistors used to implement the following CMOS gate so the delay is not worse than a basic inverter. Assume that for a reference inverter: (W/L)n = n = 1.5, and (W/L)p = p = 3. Finally, the channel length (L) of all transistors is 90 nm.
Given the circuit shown in the fig. 20.1 where VDD = 5 V, VTN = 2.5 V, μnCoxW/L = 0.5 mA/V2, and RD = 500 Ω. The operating point of this N−EMOS(IDQ, VDS) (A) (2 mA, 4.5 V) (B) (2 mA, 3.8 V) (C) (1 mA, 4.05 V) (D) (1 mA, 4.50 V) (E) None of the above Ans: D 98) Given the circuit shown in the fig. 20.2 where VDD = 12 V, R1 = 150 KΩ, R2 = 50 KΩ, RD = 10 KΩ, RS = 0, VTN = 2 V, and μnCoxW/L = 2 mA/V2. This N−EMOS has the Q point (IDQ, VDSQ) of (A) (1 mA, 2 V) (B) (0.5 mA, 4 V) (C) (0.5 mA, 5 V) (D) (1 mA, 3 V) (E) None of the above Ans: A 99) Given the circuit shown in the fig. 20.2 where VDD = 12 V, R1 = 150 KΩ, R2 = 50 KΩ, RD = 10 KΩ, RS = 0, VTN = 2 V, and μnCoxW/L = 2 mA/V2. This N-EMOS has the transconductance gm of (A) 0.001 S (B) 0.002 S (C) 0.003 S (D) 0.004 S (E) None of the above Ans: B 100) Given the current mirror circuit shown in the fig. 20.3 where 5(μnCox)M1 = 3(μnCox)M2;VTN, MI = VTN, M2; λMI = λM2 = 0. If I2 = 2 IR, then (W/L)M2 /(W/L)M1 is (A) 3 /10 (B) 10 /3 (C) 6 /5 (D) 5 /6 (E) None of the above
In the circuit shown in Fig. 3, assume that transistors M1 A and M1 B are perfectly matched and that ro = ∞. The elements labeled Ix are ideal DC current sources. (a) Assume the two transistors are biased in the saturation region that the VGS of the transistors is known. Find expressions, in terms of component values and relevant transistor parameters, for the dc voltages and dc currents at the drain, gate, and source transistor terminals. (b) Draw the the differential-mode half-circuit small-signal schematic for this circuit. Then find the differential-mode gain Adm. (c) Draw the the common-mode half-circuit small-signal schematic for this circuit. Then find the common-mode gain Acm. Figure 3
D14.1 Design the inverter in Fig. 14.12 (a) to provide VOL = 90 mV and to draw a supply current of 30 μA in the low-output state. Let the transistor be specified to have Vt = 0.4 V, μnCox = 125 μA/V2, and λ = 0. The power supply VDD = 1.8 V. Specify the required values of W/L and RD. How much power is drawn from VDD when the switch is open? Closed? Hint: Recall that for small vDS, rDS ≃ 1 /[(μnCox)(W/L)(VGS − Vt)] Ans. 1.9; 57 kΩ; 0; 54 μW (a)
b) Figure Q4 b shows a common-source amplifier circuit. The amplifier has a gm of 4 mA/V2 and the transistor's internal resistance and capacitance as follows: ro = 150 kΩ, Cgs = 10 pF, and Cgd = 1 pF. Determine: i) The mid-band gain AM ii) The lower 3-dB frequency fL by assuming fLG as the dominant frequency (associated with the coupling capacitor Ci ). iii) The upper 3-dB frequency fH. Figure Q4 b
The cross section of a p-type enhancement mode MOSFET is shown in the following figure. Determine the source-to-drain voltage required to vias a p-channel enhancement-mode MOSFET in the saturation region. It is given that Kp = 0.2 mA/V2, VTP = −0.50 volt, and iD = 0.50 mA.
source configuration with an ideal dc current source connected to its collector as shown in Fig. 2. Assume that the transistor is biased in the forward-active region. Do not ignore ro for this problem. (a) Draw the small-signal diagram for this circuit and label the input and output voltages. (2 points) (b) Find the small-signal voltage gain vout/vin in terms of the small-signal parameters gm and ro. (3 points) (c) Express your answer to part (b) in terms of appropriate dc biasing and transistor model parameters. (3 points) (d) Explain why it would be difficult in practice to bias this circuit's de operating point such that the transistor is in the saturation region. (2 points)
Fig. 1 Simple Logic Circuit Task 1: What is the logic function of simple logic circuit in Fig. 1? Task 2: What is the aspect ratio (W/L) for all the NMOSFETs in the circuit (total 4 NMOSFETs)? Please note that the VOUt is assumed to be 0.1 V, 0.05 V and 0.01 V respectively. Please calculate the aspect ratio (W/L) for all the NMOSFETs under different VOUT (0.1 V, 0.05 V and 0.01 V). The process parameters for the design are listed in Table 1. Table 1: Process Parameters Task 3: 4-mask process is applied for the manufacturing of the NMOSFET. It is required to provide the process flow from step one till the last step. Each step shall have its top view and cross-section view. Please take NMOSFET C as an example (W/L ratio upon VOUT = 0.05 V).
(i) Design a CMOS logic circuit to implement the function Y = AB + C¯. Find the minimum width for each transistor such that the delay is not worse than the reference inverter. Assume that for the basic inverter n = 2 and p = 4 and that technology used is L = 0.5 μm. ( 8 marks) (ii) Consider the circuit shown below. (a) Express Y as a function of A and B. (b) Redraw the circuit using CMOS Transmission gate switch. (c) Compare the performance of the Transmission Gate switch to the NMOS switch and PMOS switch. (6 marks) (iii) Mark the correct answer in the following. (6 marks)VIH is a) the maximum input voltage level to be considered as High. b) the maximum input voltage level to be considered as Low. c) the minimum input voltage level to be considered as High. d) the minimum input voltage level to be considered as Low. VIL is a) the maximum input voltage level to be considered as High. b) the minimum input voltage level to be considered as Low. c) the minimum input voltage level to be considered as High. d) the maximum input voltage level to be considered as Low. The noise margin in the Low state for a logical circuit with VIH = 2.2 V, VIL = 0.4 V, VOH = 4.0 V and VOL = 0.2 V is a) 0.2 V. b) 2.0 V c) 1.8 V. d) 3.6 V.
a) Design a CMOS logic circuit to realize the following function Y = A¯B¯C + A¯BC¯ + AB¯C¯ by constructing both the Pull Up Network (PUN) and Pull Down Network (PDN). [6 points] b) Provide the W/L ratios for each transistor in the logic circuit obtained in a). Assume that for the basic inverter n = 2, p = 4 and L = 0.5 μm. [3 points ] c) Design a pass-transistor-logic circuit (transmission gate) to realize the function Y¯ = AB + A¯B¯. [3 points] d) Define the following parameters; and find them from the shown VTC [3 points ] i) VIH ii) VIL iii) NML iv) NMH
Draw a supply independent current reference circuit using MOS current mirrors with ratio K and a resistor Rs. i. Calculate the output current Iout of your reference assuming K = 10, Rs = 10 kΩ, β = 100 μAV−2 and Vth = 0.7 V ii. Explain what variability you would expect in the current due to process parameters, mismatch and temperature.
The C-V curve for a MOS capacitor is shown, and has the following measured data points: At point A: C = 10.4 pF, Vg = −1.03 V At point B: C = 1.1∗4.6 pF, Vg = 0 V At point C: C = 4.6 pF, Vg = 0.74 V At point D: C = 4.6 pF, Vg = 1.37 V At point E: C = 10.4 pF, Vg = 1.37 V Based on this measured data, what is the thickness of the gate oxide in Angstroms? Assume that the area of this MOS capacitor is 1307 μm^2. Use: εs = 11.7, ε0x = 3.9, and ε0 = 8.854×10^−14 F/cm. (Note that 1 Angstrom = 1 x 10^−10 meters = 1×10^−8 cm)
An ideal MOS capacitor with an n+ polysilicon gate has a silicon dioxide thickness of tox = 12 nm = 120 Å on a p-type silicon substrate doped at Na = 1016 cm3. Determine the capacitance Cox, CFB′, Cmin′, and C′ (inv) at (a) f = 1 Hz and (b) f = 1 MHz. (c) Determine VFB and VT. (d) Sketch C′/Cox versus VG for parts (a) and (b).
C-V curves derived from two MOSCAPs with the same gate area are compared below. The MOS-cap exhibiting curve b has (choose one: a thinner, the same, a thicker) oxide and (choose one: a lower, the same, a higher) doping than the MOScap exhibiting curve a. Briefly explain how you arrived at your chosen answers. Cox is the same. Cdep must be changing, which is why Cmin are different. Note that VT is also different.
A MOS capacitor has a P+ polysilicon gate and an N-type body doped with phosphorus at a concentration of 9.4 x10^16 /cm^3. If this capacitor is operating in depletion with a depletion region width of 34 nanometers, then what is the surface potential in millivolts? Use: εs = 11.7, εox = 3.9, ε0 = 8.854×10^−14 F/cm, and q = 1.6 x 10^−19 C. For this question, be sure to give your answer to the nearest millivolt!
What is the threshold voltage in millivolts for a MOS capacitor with an N+ polysilicon gate and a P-type body doped with boron at a concentration of 2 x10^16 /cm^3 ? Assume that the oxide thickness is 77.7 angstroms. Use: kT/q = 26 mV and ni = 1.5×10^10 /cm^3 at 300∘K, εs = 11.7, εox = 3.9, ε0 = 8.854×10^−14 F/cm, and q = 1.6×10^−19 C. Assume that the intrinsic Fermi level, Ei, is in the middle of the band-gap, and use Eg = 1.12 eV. For this question, be sure to give your answer to the nearest millivolt! Answer: The correct answer is: -36
What is the flat-band voltage in millivolts for a MOS capacitor with an N+ polysilicon gate and a P-type body doped with boron at a concentration of 3.5×10^17 /cm^3 ? Use: kT/q = 26 mV and ni = 1.5×10^10 /cm^3 at 300∘K. Also use Eg = 1.12 eV and Xsi = the electron affinity = 4.05 eV for silicon. Assume that the intrinsic Fermi level, Ei, is in the middle of the band-gap. For this question, be sure to give your answer to the nearest millivolt! Answer: The correct answer is: -1001
A MOS capacitor has an N+ polysilicon gate and a P-type body doped with boron at a concentration of 5.9×10^17 /cm^3. The thickness of the gate oxide is 41 angstroms. If this capacitor is operating in depletion with a depletion region width of 37 nanometers, then what is the voltage across the oxide in millivolts? Use: εs = 11.7, εox = 3.9, ε0 = 8.854×10^−14 F/cm, and q = 1.6×10^−19 C. For this question, be sure to give your answer to the nearest millivolt! Answer: The correct answer is: 415