Electrical Engineering Archive: Questions from 2024-05-21

5.51 Consider the circuit of Fig. 5.24(a). In Example 5.6 it was found that when Vt = 1 V and kn′(W/L) = 1 mA/V2, the drain current is 0.5 mA and the drain voltage is +7 V. If the transistor is replaced with another having Vt = 1.5 V with kn′(W/L) = 1.5 mA/V2, find the new values of ID and VD. Comment on how tolerant (or intolerant) the circuit is to changes in device parameters. ^ Hide Answer 0.454 mA, +7.28 V; circuit is quite tolerant to variations in device parameters (a)

What is the output resistance, rds, in kΩ for an NMOS FET operating in saturation with Id = 195 μA ? Use: λ = 0.07 Answer. The correct answer is: 73.26

Question 2. Current calculations in 180 nm node MOSFET transistor technology II You may assume the following data in the usual notation. Equations for the drain current can be found in the notes. VDD = 1.8 V, Vtn = 0.5 V, Vtp = −0.5 V and λn = |λp| = 0.2 V−1. Take kn = 4kp with kn = 300 μA/V2, where k is the process transconductance parameter. L = 0.18 μm, (W/L)n = n = 1.5 and (W/L)p = p = 6. (a) How much drain current flows in an n-channel MOSFET when Vgs = 0.7 V and Vds = 0.1 V ? Express the drain current as the drain current per μm device width. (b) How much drain current flows in a p-channel MOSFET when a voltage of 1.1 V is applied to gate electrode and 1.7 V applied to the drain electrode? Comment on your answer in relation to the result in part (a). (Hint: in this question you are not give the potential differences). (c) Ignoring the effects of channel length modulation, how much drain current flows in an nchannel MOSFET when Vgs = 0.7 V and Vds = 0.8 V ? How would your answer change if channel length modulation effects are taken into consideration?

Question 1. Current calculations in 180 nm node MOSFET transistor technology I An n-MOSFET is fabricated in 0.18 μm technology characterized by the following process and device parameters: VDD = 1.8 V, Vtn = 0.5 V, L = 0.18 μm, Wn = 0.27 μm and a SiO2 thickness of 4 nm, in the usual notation. Take the relative dielectric constant of SiO2 to be 3.9 and ε0 to be 8.85 ×10−12 F/m. (a) What is the process transconductance parameter, kn, if the electron mobility is 400 cm2 /Vs. Express your answer in A/V2 and μA/V2. Explain why the units of kn are A/V2 or μA/V2. (b) If the mobility of holes in silicon is 1 /3 that of electrons, by what factor will kp differ from kn ? Why is this important? (c) What is the capacitance per unit area (Cox) for a 10 nm thick SiO2 ? The SI unit of areal capacitance is F/m2 but device engineers often use F/cm2 or fF/μm2. Express your answer in both these units as well. Instead of calculating the capacitance per unit area again for different oxide thicknesses device engineers may employ a scaling argument. How would your answer above change if the oxide thickness was (i) increased to 20 nm, (ii) reduced to 3 nm or (iii) reduced to 1 nm (d) How much drain current flows in the transistor if VDS = 0.2 V and VGS = 0.8 V ? Express your answer in μA per micron of device width. Why do you think it is useful to express the drain current as the drain current per μm device width?

Assume IB1 is implemented using a MOSFET, VTH = 0.4 V, and Vov = 0.1 V. Find minimum VB. If VB is set at 0.1 V above the minimum value, find Vin,min and Vout,min.

Consider an n-channel enhancement-mode MOSFET with the following parameters: VTN = 0.4 V, W = 20 μm, L = 0.8 μm, μn = 650 cm2/V−s, tox = 200 Å, and ϵox = (3.9)(8.85×10−14) F/cm. Determine the current when the transistor is biased in the saturation region for (a) vGS = 0.8 V and (b) vGS = 1.6 V.

In the op amp circuit given below, find the closed-loop gain and phase shift of the output voltage with respect to the input voltage if C1 = C2 = 1 nF, R1 = R2 = 100 kΩ, R3 = 20 kΩ, R4 = 23 kΩ, and ω = 2000 rad/s. (VS = 10 V) Please report your answer so the magnitude is positive and all angles are in the range of negative 180 degrees to positive 180 degrees. VO/VS = < ∘

Determine the voltage gain and the signal waveforms at various points. Assume that CC1 and CC2 are very large. β = 100, VA = 100 V. (a) Find the dc voltages at the base, emitter, and collector. (b) Find gm, rπ and r0. (c) If terminal Z is connected to ground, X to a signal source vsig with a source resistance Rsig = 2 kΩ, and Y to an 10−kΩ load resistance, use the hybrid−π model to draw the small-signal ac equivalent circuit of the amplifier. Calculate the overall voltage gain vy/vsig .

For the cascaded system of Fig. with two identical stages, determine: a. The loaded voltage gain of each stage. b. The total gain of the system, Av and Avs. c. The phase relationship between Vo and Vi

Assuming an infinite load resistance, calculate the gain of the amplifier below, given that I0 = 1.5 mA, Vcc = 10 V, Vee = −10 V, The early voltages of T1 and T2 are 132 and the early voltages of T3 and T4 are 71 Giving your answer to 2 decimal places Correct Answer: 1,846.70

Problem 2) Differential pair, BJT biasing In the above circuit, β = 100. a) Determine the differential gain, AvDM. b) Determine the differential mode input resistance, RinDM . c) Determine the common mode input resistance, RinCM . d) Determine the differential output resistance, Rout.

The differential amplifier provided utilizes a resistor Rss = 1.5 kΩ to establish a 1 mA dc bias current. Note that this amplifier uses a single 5 V supply and thus the dc common -mode voltage Vcm cannot be zero. Transistors Q1 and Q2 have identical parameters given by: Kn = 2 mA/V2 Vthn = 0.7 V λ = 0 Find the minimum required value of Vcm. Find the value of RD that results in a differential gain Aid of 2 V/V. Determine the dc voltage at the drains of Q1 and Q2. Determine the common-mode gain Acm. Vcm(min) = V RD = kΩ VD1 = V VD2 = V Acm = V/V

The differential amplifier circuit of Figure Q.2 utilizes a resistor connected to the negative power supply to establish the bias current I. a) For vB1 = vid/2 and vB2 = −vid/2, where vid is a small signal with zero average, find the magnitude of the differential gain, |vo/vid|. [8 marks] b) For vB1 = vB2 = vicm, where vicm has a zero average, find the magnitude of the common-mode gain, |vo/vicm|. [8 marks] c) If vB1 = 0.1 sin⁡2π×60t + 0.005 sin⁡2π×1000t volts, and vB2 = 0.1 sin⁡2π×60t − 0.005 sin⁡2π×1000t volts, find vo. [4 marks] Figure Q. 2

Fig. 3 shows a pnp differential amplifier, where R1 = R2 and RA is the output resistance of the current source IA⋅Q1 and Q2 are identical with β = 100 and VA → ∞. The circuit is designed so that Q1 and Q2 are biased in the active region. a) What is the main advantage of a differential amplifier over a single-ended amplifier? (3%) b) Express the rπ and gm of Q1 and Q2 in terms of IA⋅RA is ignored here. (4%) c) Draw differential-mode AC half circuits of the amplifier. (6%) d) Find an expression for the differential-mode input resistance. (3%) e) Find an expression for the differential-mode gain (vop−vom vip−vim), (3%) f) Draw common-mode AC half circuits of the amplifier. (6%)

Consider the circuit shown on the left. VCC = VEE = 14 V. IEE = 0.1 mA. REE = 190 kΩ. RC = 100 kΩ. The two BJTs are identical with β = 100. The two MOSFETs are identical with K = 170 μA/V2 and |VT| = 2 V. v1 and v2 are pure ac sources. Determine the ratio vo v1−v2. (This ratio is called the differential gain).

The circuit below is a BJT differential amplifier with VCC = VEE = 3 V. The DC current source IEE is assumed ideal. The two transistors are identical, operate in the active region, and have α = 0.99 and VA = ∞. The thermal voltage VT is 26 mV at room temperature. The input is purely differential, i. e. , vip = −vim = vid/2 a) Draw small-signal differential-mode half circuits of the differential amplifier. (5%) b) Express the differential voltage gain Ad, which is defined as (vop − vom)/vid, in terms of IEE, RL, α and VT⋅(6%) c) If IEE = 2 mA, what should be the value of RL to achieve Ad = 40 ? (4%) d) Choose another set of IEE and RL to maintain Ad = 40 while reducing the power consumption by half compared to the situation in part c). (2%) e) What is the maximum Ad that the circuit can achieve if the DC levels at the output nodes vop and vom must be equal to or higher than 0 V? (3%)

(a) Figure Q2(a) shows a differential amplifier with a current source at the bottom. It is given that VDD = VSS = 15 V, ISS = 300 μA, Early effect can be ignored (λ = 0), Kn = 400 μA/V2 and VTN = 1 V. You may assume MOSFET in saturation region. (i) For single ended outputs, draw the half-circuits and derive the algebraic equations for the differential mode and common-mode gains as well as CMRR. [6 Marks ] (ii) For the above case of single ended output, what should be the value of Rss to get CMRR = 100? [4 Marks] Figure Q2(a)

In the following network, draw the equivalent small signal circuit and determine Rin, Rout and Voltage Gain (AV) by showing the calculation steps.

For the amplifier network shown in the figure, neglect the re value, the input voltage has an amplitude of 1 V and frequency 1 kHz, the amplifier gain is

In the circuit shown in figure 3 , assume Iss = 1 mA, and W/L = 50/0.5 for all transistor. The ratio of current through M5 over M3 and M6 over M4 are both 4:1. μncox = 350 μA/V2; μpcox = 100 μA/V2, Vtn = Vtp = 0.8 V. a) Determine the voltage gain (all transistors are in saturation region). b) Calculate Vb such that ID5 = ID = 0.8 (Iss/2). c) If the current source IsS requires a minimum voltage of 0.4 V, what is the maximum differential output swing? Figure 3

Q2. Consider the differential amplifier where the load is a capacitor Co and the output voltage is taken differentially across Co. Let gm = 1.25 mS, RD = 1 KΩ, RSS = 1 MΩ, Co = 12π nF You are asked to: a) Draw the half circuit for the differential mode. b) Find the bandwidth of the differential mode in Hz. c) Draw the half circuit for the common mode. d) Find the bandwidth the common mode in Hz.

For the circuit of Fig. 2, we want to have Iout = Iin. Using Nodal analysis, find the required value of RS as a function of Iin. Assume (W/L)M4 = 4(W/L)M3. Figure 2: Tail Current

Consider the NMOS track and hold circuit from Figure I. What is the maximum input signal voltage that the circuit can track? 2. Assume that the charge accumulated in the channel during the tracking phase is ΔQ = CoxWL(VDD − Vth − Vin). Determine the resulting voltage error if half of the accumulated charge is injected to CS when the switch turns off. 3. Is the resulting voltage error linear or nonlinear? Is it signal-dependent or independent? Justify your answer. 4. Construct a model for the sampling circuit shown in Figure When the NMOS switch M1 is ON, the sampling circuit behaves as a series RC circuit and the input Vin is sampled on the capacitor. When the switch turns OFF, the voltage on the capacitor is held constant until the beginning of the next sampling phase. If the ON resistance of the switch is R, then the time constant of the sampler is τ = RCS. For an input sinusoidal signal of frequency 1 GHz, a sampling frequency of 10 GHz and time constant of 10 ps, plot the output of the sampling circuit.

(a) Determine the logic expression for the circuit shown below (b) Find out (W/L) p of the PMOS transistor such that Vout = 0.2 V. Given A = 0 V, B = 2.5 V, both the NMOS has (W/L)N = 1.5 /0.25, μN/μP = 2 and VTHn = |VTHp| = 0.5 V.

(10%) In the circuit of Fig. 1 , assume that ID1 = ID2 = 0.2 mA, (W/L)1 = 25 /0.5, (W/L)2 = 40 /2, and RsS = 1 kΩ, when both devices are in saturation. Recall that λ∝1/L when you calculate ro. Note :λ≠0, γ = 0) (a) Calculate the small-signal voltage gain Av = Vout Vin . (b) Calculate the output voltage swing while both devices are saturated. Fig. 1

Assume the op amp in the following circuit is ideal. a) Determine the voltage V1 b) Determine the voltage V2

3a. Derive the small-signal fully-differential gain of the circuit. Assume λ = 0 for all transistors. Express your answers in terms of device small-signal parameters gm1, ro4, etc. Assume M3-M6 are identical, and all transistors are biased in the saturation region. Note that M3-M6 have identical bias conditions, thus have identical small-signal parameters. 3b. Repeat with λ > 0

Calculate the fall time for the below model of CMOS under High to Low transition. Given that the value of Vout is given by the following equation: Vout = VDDe −t/RnCL (where VDD, Rn and CL are 5 V, 100 Ω and 100 pF respectively). Also, assume that the boundaries of LOW and HIGH levels are 1.5 V and 3.5 V respectively. Give your answer in terms of nanoseconds (ns) and rounded to 2 decimal places.

An op-amp circuit with two inverting amplifiers in cascade is shown with a variable resistance Rx. The input voltage is VSRC and input current is lin. Using node voltage analysis, derive an expression for the voltage gain Vout/VSRC as a function of resistor Rx. What is the voltage gain when Rx is infinite? What is the voltage gain when Rx is zero? Can you now figure out why Rx is used?

The circuit is designed based on the long-channel CMOS process. The transistor M1 with the dimension of 10/2 is drawn with a scaling factor of 1 um. The transistors are biased so that the DC values of the drain current and Vout are 20 uA and 2.5 V respectively. The supply voltage VDD is 5 V. The bodies of both transistors are tied to their respective source terminals. Sketch the small signal model of this amplifier. The parasitic capacitances Cgs1, Cgd1 and Cgs2 need to be shown. Find the gain and transfer function of the model. Find the poles and zeroes of the system.

Problem 3. (30 points): MOSFET transistor amplifierAnalyze the given circuit to find the output voltage vO on the load RL and the basic parameters for each amplifier stage (i. e. voltage gain, the input and output resistance). Given: M1: Kn' = 3 mA/V, W = 25 μm, L = 2 μm; threshold voltage VTN = 2.4 V; (*Note: you should draw the dc and ac equivalent circuit)Given that the input voltage vI frequency from 5 kHz to 150 kHz, choose coupling and bypass capacitors.

Single Stage Integrated-Circuit Amplifier Part I PMOS Current Mirror Figure 1 Draw the circuit in Fig 1 using the Mbreakp1 PMOS model file provided. Run a bias simulation which shows all the voltages and currents at each node of the circuit. Print out the circuit displaying all the currents and voltages. Running a bias simulation: (PSPICE - > new simulation profile - > under analysis type, choose Bias Point - > run simulation and look on your schematic). In general, what is the purpose of a current mirror in IC design? What current value is being mirrored? Change the (W/L) ratio of the PMOS to (20 e-6 /1 e-6) by changing the Model File. Ex. . model Mbreakp PMOS +W = 20e−6 +L = 1 e−6 What is the current value being mirror? Now decrease the width by half. What effect does that have on the current, if any?

Problem 4: Consider the logic path shown below. Assume it is designed in a technology with μNMOS/μPMOS = r = 2. (a) Use the method of logical effort to find the size factors 'a', 'b', and 'c' to minimize the delay through this logic path. Note that, the size factors 'a', 'b', and 'c' are about the input capacitance C of a single input of the first stage (which is a 3 input NAND gate). The load capacitance is also about C. (b) Now assume that the first stage is designed such that its pull-down resistance is same as that of an inverter designed with the minimum size NMOS devices (Wmin having a capacitance of CMIN). What should be sizes of the NMOS and PMOS devices (with reference to the minimum size NMOS devices) of the different stages to achieve the minimum delay found in part (a)? Fill up the table below with the results.

Circuit diagrams of six different single-stage common-source amplifiers. In the circuits Vdd = 5 V, (W/L)1 = 100, (W/L)2 = 250, Vb = 4 V, Vb1 = 2.5 V, RD = 500 Ω, RS = 500 Ω, Vin = 2 + 0.01 sin⁡(2000πt + 90∘)V Fig. 1. Fig. 2. Fig. 3. (a) Find out the bias points (DC node voltages and branch currents) of the circuits. If any of the transistors are not in the expected region of operation, modify the circuits by changing the aspect ratios of the transistors for the proper functionality. (b) Calculate the small signal gain, input resistance, and output resistance of the circuits. (c) Plot Vin and Vout for 3 ms and neatly label it. (d) Calculate Vout,max and Vout,min, and hence the maximum output voltage swing of the amplifiers. Using this find out what is maximum allowable input voltage swing. By changing the aspect ratios of the transistors, can you obtain the maximum possible voltage swing? (e) Can you increase the gain of the amplifiers by a factor of 2 just by changing the aspect ratios of the transistors? (f) Repeat (a)-(e) assuming the second order effects are present in the transistors.

The parameters of the circuit shown are VDD = 3,3 V and RD = 5 kΩ. The transistor parameters are kn′ = 100 μA/V2, W/L = 40, VTN = 0, 4 V and λ = 0, 025 V−1. a) Find IDQ and VGSQ such that VDSQ = 1, 5 V. b) Determine the small-signal voltage gain.

4.22 For the common-source amplifier in Figure P4.22, the transistor parameters are VTN = −0.8 V, Kn = 2 mA/V2, and λ = 0. The circuit parameters are VDD = 3.3 V and RL = 10 kΩ. (a) Design the circuit such that IDQ = 0.5 mA and VDSQ = 2 V. (b) Determine the small-signal voltage gain. Figure P4.22

A common-drain amplifier is shown. The circuit parameters are RS = 4 kΩ, R1 = 850 kΩ, R2 = 350 kΩ and RL = 4 kΩ. The transistor parameters are VTP = −1,2 V, kp′ = 40 μA/V2, W/L = 80 and λ = 0,05 V−1. a) Determine IDQ and VSDQ. b) Determine the small-signal voltage gain Av = vo/vi. c) Determine the small-signal circuit transconductance Ag = io/vi. d) Find the small-signal output resistance Ro.

We would like to analyze the circuit given in Fig. 1. This circuit consists of two PMOS transistors in which one of them is in saturation. It is important that other remains in the saturation region for this mirror to work.

Consider the following two designs of an 8-input AND function. Assume μn = 2μp. For each design, size the transistors such that the delay is minimum. Specify the width of the pMOS and nMOS transistors as a function of W0, where 3W0 = Cin = 1.

Problem 1: Consider the logic circuit below to the left: (a) What is the logic function implemented by the design below? (b) Size NMOS and PMOS devices in the circuit below so that the worst-case pull-up and pull-down strength of the circuit is exactly as much as in the inverter shown to the right. Assume that all the transistors in the circuit above and in the inverter have a minimum channel length (LMIN). In the inverter, the width of NMOS is WMIN and PMOS is 2×WMN. (c) For the logic design, identify the transition for the worst case 'high to low' and 'low to high' delay considering that only one of the input (among A, B, C) switches. Compute RC delay for these transitions. Assume that the resistance of a minimum width width (WMIN), the junction capacitance is C at each source and drain ends. Ignore any external load capacitance for the circuit.

Both MOSFETs in the circuit shown have VT = 1 V and k = 4 mA/V2. The voltage vA is given by vA = 0.4 + 0.1sin⁡(2πt) where t is in ms and vA is in V. Determine v0.

Problem 1: MOS Threshold Voltage (Following problem 3 of homework 4) Consider an ideal MOS capacitor maintained at T = 300 K with the following parameters:Gate material is p+ polycrystalline-silicon (work function ΦM = 5.2 eV ) Substrate is n-type Si, with doping concentration 1018 cm−3 (assume that this is nondegenerate) Oxide thickness x0 = 2 nm a) What is the threshold voltage, VT, of the MOS capacitor? b) What is the maximum width of the depletion region, WT ? c) Indicate qualitatively how your answers to part (a) would change if the substrate doping ND were to be decreased (e. g. to 1017 cm−3 ). d) Indicate qualitatively how your answers to part (a) would change if the oxide thickness xo were to be increased (e. g. to 3 nm ).

Problem 2: MOS Areal Charge Density Consider an n+ poly-Si-gated MOS capacitor with oxide thickness x0 = 3 nm and p-type Si substrate doping NA = 1017 cm−3 maintained at T = 300 K. (Gate work function ΦM = 4.1 eV ) a) What is the flat-band voltage, VFB, of this capacitor? b) What is the threshold voltage, VT, of this capacitor? c) Write down formulae for the total areal charge density (in C/cm2 ) in the Si as a function of gate voltage, for each of the regions of operation (accumulation, depletion, and inversion). Plot the total areal charge density as a function of VG > VFB. d) Calculate the areal charge density in the Si for a gate voltage VG = VT + 1 V, and sketch the corresponding charge distribution within the MOS structure for this gate bias.

Taks 1 : Design a telescopic cascode amplifier as shown in diagram where sizes of all MOSFETs are same. VDD = 1.8 V. The output voltage swing is 0.272 V and overall power dissipation is 270 μW. Calculate sizes of MOSFETs and bias currents. What is the gain of amplifier?

Design the current mirror circuit to provide nominal output current I0 = 80 μA based on the reference MOS current mirror as shown Figure 1 with VDD = 1.2 V and IREF = 10 μA. Q1 and Q2 have equal channel lengths L = 0.4 μm, equal Vtn = 0.4 V, kn′ = 400 μA/V2, and the width of Q1 is wQ1 = 1 μm. (a) Find the value of R and W2. (12 marks) (b) Assuming Early voltage VA′ = 6 V/μm, find the output resistance of the current source. ( 13 marks) Figure 1