Consider the circuit shown below. a) what are the required values for RS and RD to establish a drain current of 0.1 mA and a drain voltage of +0.4 V. The MOSFET has Vt = 0.5 V, μnCox = 300 μA/V2, L = 0.4 μm, and W = 5 μm. (8 marks for each parameter) b) If Vt = 0.3 V and kn = 5 mA/V2. The voltages at the source and the drain are measured and found to be −0.6 V and +0.2 V, respectively. What current ID is flowing ( 8 marks), and what must the values of RD and RS be? ( 8 marks for each parameter) What is the largest value for RD for which ID remains unchanged from the value found? ( 10 marks)
Assume the circuit where M1 and M2 operate in saturation and exhibit channel-length modulation coefficients (λn and λp), transconductances (gmn and gmp), output resistance ( ron and rop) respectively. Please answer the following questions. (a) What is the difference between the MOSFET output curves (drain current vs. drain voltage) with and without channel-length modulation effects? (b) Draw the small-signal equivalent circuit of the figure below at low frequency. (c) Determine the small-signal voltage gain of the circuit below. (d) If finite resistance R5′s are added to the source terminals of M1 and M2 in series, will the small-signal voltage gain increase, decrease, or remain the same?
Plot the input/output characteristic of the XOR PD for two cases. To receive full credit, you must show the minimum and maximum values on the graphs. Note that Xout is the average output of the PD. (a) The circuit has a single-ended output that swings between 0 and VDD. (b) The circuit has a differential output that swings between −V0 and +V0. Use a graph similar to the one depicted below for both parts.
(20 points) The following shows the NFET network of a static CMOS logic design. Express y as a Boolean function of the input signals ai, bi, ci.
Implement the function f = x1x2 + x¯2x3 with any number of the chips referenced in Problem 7. That is, draw the components with their physical characteristics (as shown in Fig. 3) but label all their chips with their part numbers and connect pins appropriately. Don't forget VDD and GND ! Figure 3
Design the current mirror circuit to provide nominal output current I0 = 80 μA based on the reference MOS current mirror as shown Figure 1 with VDD = 1.2 V and IREF = 10 μA. Q1 and Q2 have equal channel lengths L = 0.4 μm, equal Vtn = 0.4 V, kn′ = 400 μA/V2, and the width of Q1 is WQ1 = 1 μm. (a) Find the value of R and W2. (b) Assuming Early voltage VA′ = 6 V/μm, find the output resistance of the current source. Figure 1
Fig. 3 Figure 3 shows a MOS current mirror biased with a dc input ID1 and fed with a small-signal input current i. VGS and ID2 are the dc quantities, while vgS, and i0 are signal quantities. Show the small-signal equivalent circuit of the mirror circuit using all the small-signal quantities (Rin, Ro, r01, gm1, gm2, vgs, r02, i0). [25]
Using the op-amp configuration shown in Figure 1, answer the problem below: Figure 1 The required voltage gain (vo/vi) of the amplifier shown in Figure 1-2 is -20 V/V. The open loop gain of the op-amp is 800 /v. If R1 = 10 kΩ and R2 = 200 kΩ, what is the value of Rc to meet the specifications given? All other non-idealities of the op-amp (offset voltage, input bias current, offset current) can be considered negligible. Enter your answer in kΩ.
Q. 4: Figure 4 depicts an MOS device based differential amplifier using active loads. Figure 4: (a) Draw the schematic of a similar differential pair amplifier using BJT devices. Assuming that the bias sources have infinite output resistances, find the small signal voltage gain vout/(vin1 − vin2) of the BJT based differential pair. You can use the half-circuit principle. The ac signals Vin1 , Vin2 form a balanced differential input signal pair. (b) It is given that Iss = 2 mA, Iss2 = 1 mA, VDD = 5 V, and the Early voltage VA = 50 V for all the transistors. The transistors are all identical.
for the follower circuit above, Rsig = 2 Kohm, R1 = 202 Kohm, R2 = 196 Kohm, Rc = 3 Kohm, R3 = 0.7 Kohm, R6 = 3.9 Kohm. if the transistor has gm = 1.1 mS and C3 is used for dominant pole design of lower corner frequency f = 3 KHz. determine the value of for the follower circuit above, Rsig = 2 Kohm, R1 = 202 Kohm, R2 = 196 Kohm, Rc = 3 Kohm, R3 = 0.7 Kohm, R6 = 3.9 Kohm. if the transistor has gm = 1.1 mS and C3 is used for dominant pole design of lower corner frequency f = 3 KHz. determine the value of C3 in nF C3 in nF
8.91. (a) Find the Q-point, voltage gain, input resistance, and output resistance of the amplifier in Fig. P8.91. if R1 = 240 kΩ, R2 = 750 kΩ, R3 = 100 kΩ, K′n = 100 μA/V2, VTN = 1 V, λ = 0.02, (W/L)1 = 5/1, (W/L)2 = 5/1 and VDD = 9 V.
The amplifier circuit shown in Figure B3 has a gain of -5. (a) Calculate the feedback resistor, Rf. (2 marks) (b) Calculate the peak output voltage, Vout(p). (2 marks) (c) Sketch the input and output waveforms on a common x-axis and indicate the peak values. (4 marks) (d) State the changes to the output waveform if the input voltage is increased to 8 V(p−p). (2 marks) Assume +Vsat = 13 V and −Vsat = −13 V Figure B3
Figure 1: Circuit for problem 1. In Fig. 1(a), determine the signs on the opamp for negative feedback operation. Determine the gate potentials of the transistors for Vref = 3 V and Vdd = 7 V. Repeat for Vref = 3 V and Vdd = 5 V. In Fig. 1(b), determine the signs on the opamp for negative feedback operation. Determine the gate potentials of the transistors for Vref = 3 V and Vdd = 6 V. Repeat for Vref = 3 V and Vdd = 2.2 V.
Given V2 = 6 vpp, Vout = 12 vpp and Rf = 3 kΩ, find the value of R1 (in Ω ) and the transfer function (in v/v). Write the transfer function in phasor notation. Input resistor = kΩ. (Round your answer to 2 decimal places) Transfer function = at an angle of ∘v/v. (Round your answer to 2 decimal places. Write the magnitude as a positive number.)
Example Determine the output resistance of the circuit in Fig. 7.19(a) and compare the result with 7.10 that in the above example. Assume M1 and M2 are in saturation. (a) (b) Figure 7.19 (a) Example of CS stage with degeneration, (b) simplified circuit.
Q. 2. Figure Q. 2 shows a voltage divider circuit using n-channel E-MOSFET which has K = 5 mA/V2 and VGS(TH) = 2 V. If VDD is 20 V and RD is 1.2 kΩ, a. Determine ID if VD is given as 10 V. b. Calculate VGS. c. Calculate the values of RS and R2 required to bias the MOSFET amplifier at VGS = 1/3 VDD. d. Determine the value of VDS.
Q. 4. Figure Q. 4 shows a common source (CS) E-MOSFET with a drain feedback bias amplifier circuit. Given VGS(TH) = VTH = 3 V and k = 0.24 mA/V2. Determine the Q-point (IDQ and VGSQ) graphically. Figure Q. 4
[ Problem 2] (5+5+10+10) For the following function f = x¯2 + x1x¯3 + x1x2x4 (a) Optimize the gate level design by using only 2-input NAND gates. Then, count total number of transistors. (b) Design CMOS circuit that minimizes the number of transistors. Then compare the number of transistors and its critical path delay with that of circuit in (a). (c) Optimize the design using FPGA utilizing 2-input LUT's. How many cells are used? (d) Implement it using 3-to-1 multiplexers only. It needs to select optimized one after investigating all possible implementations.
9.47 For the circuit shown in Figure P9.47, determine vo(t), where vin (t) is as shown in Figure P9.44. Let β = 120, RB = 10 kΩ, RC1 = RC2 = 1 kΩ, and VCC = 4 V. Figure P9.47
In the following network, draw the equivalent small signal circuit and determine Rin , Rout and Gain (AV) by showing the calculation steps.
An electrical engineer designed an RL circuit similar to the one shown in the figure, with ε = 6.00 V, L = 2.00 mH, and R = 7.80 Ω (a) What is the inductive time constant of the circuit (in ms)? ms (b) Calculate the current in the circuit (in A) 250 μs after the switch is closed. A (c) What is the value of the final steady-state current (in A)? A (d) After what time interval (in ms ) does the current reach 80.0% of its maximum value? ms
Question 3 (2.5 pts) : Find vx(t), t ≥ 0 for L1 = 20 mH, L2 = 80 mH, C3 = 10 mF, C4 = 90 mF, R5 = 2 Ω, I6 = 1 A. The initial currents of the inductors are i1(0) = 0.2 A, i2(0) = 0.4 A, and the initial voltages of the capacitors are v3(0) = 2 V, v4(0) = 1 V.
Experimental Work: Specify the drain and source pins for each transistor in the XOR logic gate given in figure 1. Describe the method of operation of the circuit. Write the network list of XOR pass transistor design given in figure 1 using table 1 and table 2 parameters. Figure 1. Pass Transistor XOR Gate
Identify the feedback topology of the amplifier shown in Figure Q3c and hence the amplifier type. Represent the circuit as a negative feedback system and hence estimate the appropriate gain. State any approximations used in your analysis.
For the circuit shown below, assume node "Out" was initially at 0 V and is being charged by the PMOS shown in the figure. (Assume the width of transistor is W and threshold voltage is VT, also all the parasitic capacitances associated with the transistor are negligible. ) a) (3 Points) Derive the expression for the total energy supplied by the voltage source VDD during the charging process. b) (2 Points) How would the total energy supplied by the voltage source VDD change if the transistor VT is increased by 25% ? c) (2 Points) How would the total energy supplied by the voltage source VDD change if the overdrive voltage i. e. (VSG-|VT|) is increased by 25% by pulling the gate terminal to a negative voltage? d) (2 Points) How would the energy supplied by the voltage source VDD change if the value of VDD is increased by 25% ? e) (3 Points) Derive the expression for the total energy supplied by the voltage source VDD if the PMOS is replaced by NMOS (and the gate of NMOS is connected to VDD). Assume zero current through the NMOS in cut-off region.