9.20. Compute the short-circuit transconductance and the voltage gain of each of the stages in Fig. 9.53. Assume λ > 0 and VA < ∞. (e)
Consider the MOSFET common-source amplifier shown below: a) Using the direct analysis method, derive expressions for the location of all low-frequency poles and zeroes of the amplifier circuit's transfer function. b) Using the Miller method, derive expressions for the location of all high-frequency poles and zeroes of the amplifier circuit's transfer function. You may neglect the effects of channel length modulation in your analysis. NOTE: The midband gain of the amplifier shown above can be expressed as AMID = −gmRD 1+gmRS1
Consider the MOSFET feedback amplifier circuit shown below: a) Identify the type of feedback amplifier depicted. (5 points) b) Analyze the feedback network and determine R11, R22, and K. (10 points) c) Construct the loaded open-loop gain circuit and derive an expression for A. (10 points) d) Using the results of b ) and c), determine Af, Rif, and Rof. (10 points) You must include the effects of channel length modulation in your analysis.
Consider the MOSFET feedback amplifier circuit shown below: a) Identify the type of feedback amplifier depicted. (5 points) b) Analyze the feedback network and determine R11, R22, and K. (10 points) c) Construct the loaded open-loop gain circuit and derive an expression for A. (10 points) d) Using the results of b) and c), determine Af, Rif, and Rof (10 points) You must include the effects of channel length modulation in your analysis.
A circuit consisting of a filter and an op-amp is shown in the figure below (fig. 7). If R1 = 5 ohms, C1 = 5 farads and if the frequency of the input voltage is 4 rads/sec, calculate the voltage gain of the circuit in dBs (decibels). Insert only the numerical part of your answer without the units. Vout Fig.
The transfer function of a DC motor is given as follows. G(s) = 4 s2+2s+2 The output of the system is fed back to the input, and a proportional controller with a gain value of Kp = 4 is used as the controller. Accordingly, for w = 0.1, w = 4 and w = 100 Hz, mathematically calculate the output if the signal u(t) = 3 sin(wt) is applied to the input of the system. Create the Simulink model of the system, observe the output you get for the specified input value, compare it with the output you calculated mathematically and interpret it.
(a) Find the closed-loop transfer function, C(s)/R(s). (b) Determine the system's stability range for gain K using Routh-Hurwitz criterion. (c) What is the type of the system? (You need to convert the system to a simple unity feedback. ) (d) Sketch the root-locus in Matlab (you need to use the open-loop transfer function with K = 1) and validate the stability region you found in (b). (e) Plot the step response up to 10 seconds for the input of 1.5u(t) and the gain value that makes the system marginally stable. (f) Find the steady-state error for an input step of 1.5u(t) for K = 22 and plot this response together with the input up to 10 seconds in order to display the steady-state error you computed. (g) Find the steady-state error for an input ramp of 1.5tu(t) for K = 22 and plot this response together with the input up to 10 seconds in order to indicate the steady-state error you computed.
Exercise 2.2: Given: VBE = 0.7 V, β = 100 and VCEQ = 7.4 V. Sketch and label the DC and ac load lines. Calculate the maximum power PL(max) delivered to the load RL and the maximum power efficiency %ηmax. Answer: ICQ = 26.25 mA IC( SAT) = 41.67 mA VCE(CUTOFF) = 20 V ic(sat) = 70.39 mA Vce(cutoff) = 11.8 V PL = 32.27 mW PDC = 525 mW or 591.67 mW η% = 6.15% or 5.45%
For the common-emitter amplifier in [Figure 4-17(a)], biased at ICQ = 1.0 mA, find the time constant τE and the lower cutoff frequency fL due to the bypass capacitor CE. Assume Rs = 0.2 kΩ, RE = 4.3 kΩ, RC = 5 kΩ, CE = 50 μF, βo = 152, VCC = 10 V. Assume ro = ∞ and ignore the influence of bias resistors R1 and R2.
(a) The following measurements were made [5] on a resistive two-port circuit: With 50 mV applied to port 1 and port 2 short-circuited, the current into port 1 is 5 μA and the current into port 2 is 7 μA. With port 1 short-circuited and 10 mV applied to port 2, the current into port 1 is 12 μA while the current out of port 2 is 10 μA. Find the admittance parameters of the network. (b) Given the cascade network as shown in the figure below. The admittance parameter [11] matrix of network 1 and hybrid parameter matrix of network 2 are given. Find the voltage gain Vo Vg of the system.
For the emitter follower of Exercise 12.1 , in which I = 14.8 mA and RL = 1 kΩ, consider the case in which vo is limited to the range −10 V to +10 V. Let Q1 have vBE = 0.6 V at ic = 1 mA, and assume α≃1. Find v1 corresponding to vo = −10 V, 0 V, and +10 V. At each of these points, use small-signal analysis to find the voltage gain vo/vi. Note that the incremental voltage gain gives the slope of the vo-versus- vi characteristic. Ans. −9.36 V, 0.67 V, 10.68 V;0.995 V/V, 0.998 V/V, 0.999 V/V
We will design a differential-input single-ended-output amplifier using IBM 0.13 μm CMOS process. Below is the amplifier circuit. Follow Cadence tutorial available on elearning, start Cadence software with the IBM 0.13 μm technology file and create the above circuit in the schematic view. Set ISS = 5 μA and VDD = 2.4 V, design (1) W/L ratios of Mb1 and Mb2 such that ID, Mb2 = 10 μA and (2) W/L ratios of M1−M4 such that they all operate in the saturation region with the input common-mode voltage as 1.2 V. a. Check your DC operating points of the circuit by using DC analysis; b. Check region, vdsat, id, gm and rout of M1−M4 by using DC analysis; c. Simulate DC power consumption of the amplifier by finding total current coming from VDD and verify if it is about 36 μW; d. Based on results from (a) and (b), estimate the DC gain vo/vid of the amplifier; e. Construct the amplifier in the unity-gain feedback configuration, perform DC sweep of the input common-mode voltage from 0 to 2.4 V and then plot VO to determine the input common-mode range of the amplifier. Add a load capacitor CL of 1.5 pF at output VO, then perform AC analysis. a. Plot magnitude and phase plots of the voltage gain; b. Verify if DC gain of the amplifier matches the value obtained from your estimated value in 2)(d); c. Verify if the unity-gain frequency matches with your calculated value; d. Verify if the phase shift at the unity-gain frequency is about 90 degree.
(a) Implement the CMOS circuit for y = ABCD+E¯ and size the transistors using progressive sizing technique. Subsequently, obtain the delay expression using the RC model. (b) Explain Setup time, Hold time and Clock-to-Q delay of a D-FF with corroborative figures.
In the circuit below, the operational amplifier is ideal, R1 = R3 = 10 kΩ, R2 = 100 kΩ and E = 4.3 V. The two diodes have the current-voltage characteristic shown by the plot on the right. For −1 V ≤ Vi ≤ 1 V, a) plot Vo as a function of Vi, b) plot Vo′ as a function of Vi. Assuming vi(t) is a sinusoidal signal with an amplitude of 1 V, c) plot vo(t), (2) d) plot vo′(t). (1)
TYU 9.11 All parameters associated with the instrumentation amplifier in Fig-ure 9.26 are as given in Exercise Ex 9.8, except that resistor R2 associated with the A1 op-amp is R2 = 50 kΩ ± 5%. (a) Determine the maximum and minimum possible values of the common-mode gain. (b) Determine the maximum and minimum possible values of the differential-mode gain. (c) Determine the minimum CMRR (dB). (Ans. (a) Acm = 0; (b) Ad(min) = 5.87, Ad(max) = 156.75; (c) CMRR = ∞) Figure 9.26 Instrumentation amplifier
(2) Assume using the non-ideal Op Amp with limited gain and limited bandwidth, and the transfer function is shown below. AOL = Av0(1 + jω ω0) According to the equation, please determine the gain and the bandwidth of the circuit shown in Fig. 1. (Note that the Op Amp is not ideal, so the three principles of an ideal Op Amp may not apply. ) Fig. 1 Non-inverting Amplifier
TYU 9.15 The resistance R in the bridge circuit in Figure 9.47 is 50 kΩ. The circuit is biased at V+ = 3 V. (a) Find vO1 as a function of δ. (b) Design an amplifier system such that the output varies between +3 V and −3 V as the parameter δ varies between +0.025 and -0.025 . (Ans. (a) vO1 ≅ 0.75 δ. (b) For an instrumentation amplifier, let R4 /R3 = 10 and R2 /R1 = 7.5 ) Figure 9.47
Consider the circuit shown below. Assume the AC source has the form vs(t) = Vs cos(ωt) and the capacitors are short circuits at AC and open at DC. Assume VDD = 15 V and RS = 1 kΩ, and Vt = 1 V. Determine the operating region of the NMOS transistor and, if applicable, give an approximate value of the transconductance, gm. . Use K = 1 mA/V2; K = 12 k'WL) (points 30)Use R′s = 30 kΩ. Determine the mid-band gain of the amplifier, Av = vout vs. (points 20)Can this circuit be treated as an amplifier? If so, inverting, or non-inverting amplifier. (points 10)
An NMOS amplifier is shown in Figure 1. Transistor M1 is biased in the saturation region for an amplifier application. The circuit is biased with a resistive voltage divider consisting of R1 and R2, a source degeneration resistor RS, and a load resistor RD. The drain bias current for the design is ID = 500 μA and VDS is 1.625 V. The device parameters are: L = 0.5 μm, W = 10 μm, kn′ = 200 μA/V2, Vtn = 0.5 V, and λn = 0. CMOS 0.5 u Process . op . model NMOS1 nmos (KP = 200 u, VTO = 0.5, LAMBDA = 0) ;tran20 m Figure 1: A NMOS amplifier circuit including a source degeneration resistor RS. a) Determine R1 and R2 for the specified bias point. b) Determine the value for RD for the specified bias point. c) Use the LTSPICE circuit template and verify your bias circuit design. Include a copy of the schematic and the dc operating point results (text log with node voltages and currents). [8] d) Use LTSPICE to evaluate the change in ID for a variation in the technology process parameter kn′. Evaluate the change in ID for a change of ±10% in kn′. Compare the relative change in ID with the relative change in kn′. What do you observe? Explain how the source degeneration resistor RS implements negative feedback which reduces the sensitivity of the bias point to changes in kn′. [8]
The MOSFET in the following common-gate amplifier has Cgs = 2.0 pF, Cgd = 0.5 pF, CL = 3 pF, gm = 5 mS, Rsig = 1 kΩ, and RL = 20 kΩ. The MOSFET has a ro = ∞. Find the midband voltage gain vo/vsig. Estimate the high cutoff frequency of the circuit, fH.
The cascode in the figure below is designed to provide an output swing of 1.9 V with a bias current of 0.5 mA. If γ = 0 and (W/L)1−4 = W/L, calculate Vb1, Vb2, and W/L. What is the voltage gain if L = 0.5 μm ? Table 2.1 Level 1 SPICE models for NMOS and PMOS devices. VTO: threshold voltage with zero VSB (unit: V) GAMMA: body-effect coefficient (unit: V1/2) PHI: 2 ΦF (unit: V ) TOX: gate-oxide thickness (unit: m) NSUB: substrate doping (unit: cm−3 ) LD: source/drain side diffusion (unit: m ) UO: channel mobility (unit: cm2 /V/s ) LAMBDA: channel-length modulation coefficient (unit: V−1 ) CJ: source/drain bottom-plate junction capacitance per unit area (unit: F/m2 ) CJSW: source/drain sidewall junction capacitance per unit length (unit: F/m) PB: source/drain junction built-in potential (unit: V) MJ: exponent in CJ equation (unitless) MJSW: exponent in CJSW equation (unitless) CGDO: gate-drain overlap capacitance per unit width (unit: F/m) CGSO: gate-source overlap capacitance per unit width (unit: F/m ) JS: source/drain leakage current per unit area (unit: A/m2 )Assume VDD = 3 V and Cox = 3.8 fFμm2.
A resistively loaded PMOS inverter circuit is shown in figure Q1. The circuit is implemented with the CD4007 UBE PMOS. This is essentially the same circuit as the NMOS inverting logic gate you used in Task 3, but with a PMOS transistor instead. The load resistor RD = 6 kΩ, and the supply voltage is VDD = +5 V. The transistor parameters are μpCox = 55 μA/V2, W = 60 μm, L = 10 μm, and Vt, p = −1. For the purposes of this question ignore the channel length modulation effect, i. e. take λ = 0. a) Calculate VOUt as VIN varies from +5 V to 0 V, with 1 V steps, i. e. for 5 V, 4 V, 3 V, 2 V, 1 V and 0 V. b) What is the maximum DC power dissipated by this circuit? Figure Q. 1. Resistive load PMOS inverter circuit
5.5 For the op amp circuit of Fig. 5.44 , the op amp has an open-loop gain of 100, 000 , an input resistance of 10 kΩ, and an output resistance of 100 kΩ. Find the voltage gain vo/vi using the nonideal model of the op amp. Figure 5.44 For Prob. 5.5.
Calculate the capacitance in femtofarads on the output node of an inverter without an external load in a 0.35 μm CMOS process. Use: Wp = 6.5 μm, Wn = 4.1 μm, Lp = Ln = 0.35 μm, Loverlap = 0.1 μm, all diffusion lengths = 1.0 μm, COX = 5 fF/μm^2, Cjn = 0.9 fF/μm^2, Cjp = 1.0 fF/μm^2, Cjswn = 0.2 fF/μm, Cjswp = 0.3 fF/μm Answer: The correct answer is: 27.1
Use the following values for the transistor resistances: Rsq,n = 19 kΩ and Rsq,p = 31 kΩ. Use the following values for the capacitances: Cd = 1.9 fF/μm and Cg = 1.9 fF/μm. Problem 1: The inverters in the Figure are the same with following sizing: WN = 1.8 μm, WP = 3.6 μm, LN = LP = L = 0.6 μm. Calculate the propagation delay of the first inverter (from Vin to Vout). Simulate the inverter and compare the simulated propagation delays to calculated. Use the following parameters for the propagation delay of inverter: tpo = 45 ps and γ = 1.
The following LED driver circuit is controlled by a 100 kΩ potentiometer connected to a 10 V supply and uses an LED with the following properties: Vf = 2.4 V for the LED when If = 20 mA. Find the following (I need exact values for these unless otherwise indicated): a. Maximum and minimum current through the LED based on potentiometer position. b. Maximum voltage across the LED. c. Minimum positive supply voltage needed by the op-amp to support the maximum current through the LED (rounded up to the nearest volt). d. Maximum power dissipated by the LED and the 10 Ω resistor.
If the amplifier shown is built using resistors with a +/−5% tolerance, then what is the maximum voltage gain that might be measured in V/V ? Use nominal values for the resistors of RA = 7.7 kΩ and RB = 36.8 kΩ, and assume that the opamp is ideal. Include the sign of the voltage gain in your answer, but when determining the maximum gain only consider the magnitude of the gain, not the phase. (e. g. , A gain of −3 V/V is larger in magnitude than a gain of −2 V/V. ) Answer: Check
Work 1: Consider the system below, where we let R1 = 4 Ω, R2 = 2 Ω, and vI be an AC signal (sine function) with a peak value of 2 V and a frequency of 0.5 Hz. Problem 1: Using the characteristics of Op-Amp to identify the relationship between input and output, i. e. , vO vI = ?
Work 2: Consider the system below, where we let vI be an AC signal (sine function) with a peak value of 5 V and a frequency of 0.5 Hz. Problem 1: Using the characteristics of Op-Amp to identify the relationship between input and output, i. e. , vO vI = ?
Consider a pseudo-PMOS inverter as shown below. Derive VIL, VOH, VIH for this inverter. (Vt0,n = |Vt0,p| = VT)
Q-3: What is the propagation delay for a falling edge in pico sec for an inverter in a 0.18 μm CMOS process if the total capacitance on the output of this inverter is 75.6 fF? Use: W/Lp = 5.8, W/Ln = 16.8, VDD = 1.7 V, VTN = 0.5 V, VTP = −0.5 V, kn = 190 μA/V∧2, kp′ = 90 μA/V^2.
Q-4: Consider an inverter circuit that has FET aspect ratios of (W/L)n = 6 and (W/L)p = 8 in a process where: k'n = 160 μA/V2 k'p = 68 μA/V2 VTN = 0.75 V VTP = −0.85 V COut = 160 fF VDD = 3.8 V Compute the rise and fall times.
Q-5: What is COut in fF of a 2 -input NOR gate with no CLOAD in a 0.35 μm CMOS process. Assume NO diffusions are shared. Use: Wp = 10.0 μm, Wn = 7.5 μm, Lp = Ln = 0.35 μm, Loverlap = 0.1 μm. All diffusion lengths X = 1.2 μm, COX = 6 fF/μm2. Cjn = 0.95 fF/μm2, Cjp = 1.1 fF/μm2, Cjswn = 0.2 fF/μm, Cjswp = 0.3 fF/μm.
1.2 Spice simulationSimulate the circuit of figure 1 , connect VDD to 5 V and both inputs Vin1 and Vin2 to sinusoidal signals with an offset of 2.5 V and an amplitude of 150 mV, both signals must be out of phase. For ISS used an ideal current generator. Lets see what the gain/frequency dependency is, complete Table 1. Replace the current generator for the circuit designed in the second part of the theoretical study, repeat the analysis. Figure 1: Differential amplifier. Table 1: Amplifier differential gain vs frequency.
The inverter shown in Figure has switching voltage equal to 1.4 V. Calculate the ratio of propagation delays tpHL and tpLH (tpHL/tpLH). Use the following values for the transistor resistances: Rsq,n = 13 kΩ and Rsq,p = 31 kΩ. Use the following parameters: kn′ = 115 μA/V2, kp′ = 30 μA/V2, Vtn = 0.4 V, Vtp = −0.4 V and VDD = 2.5 V.
Problem 1. [100 pts] Biasing and small signal model of a basic differential amplifier with active load. Given the circuit below with the following conditions: Ideal voltage source VDD = 3.3 V, and ideal current source IB = 20 uA Input voltages:v2 = VCM + vd 2 v1 = VCM − vd 2 Differential input voltage: vd = v2 − v1 Common-mode input voltage: VCM = 2 VP MOS: Vt,p = −0.62 V, μpCox = 36 uA/V2, λp = 0.019[1/V]NMOS: Vt, n = 0.48 V, μnCox = 90 uA/V2, λn = 0.025[1 /V]All transistors have the length L = 2 um, except for M1 and M2 with L1 = L2 = 0.5 um. Width of the transistors: W6 = W7 = W = 4 um W5 = 2 W ∘W3 = W4 = W W1 = W2 = 8 um. Assume all transistors in saturation.