For the circuit in Figure Q1, VDD = 4 V, Iref = 0.4 mA, (W/L)1 = 1, (W/L)2 = 2, (W/L)3 = 2, (W/L)4 = 8, (W/L)5 = 24, and (W/L)6 = 6, Vpp = −1 V, and kp′ = 5 mA/V2. (a) Find Iout. (b) What are the DC voltages at nodes X and Y. (c) If |VA| = 20 V for PMOS transistors, find Rout . Figure Q1
An n-channel MOSFET has the following parameters: μn = 450 cm2 V−1s−1, tox = 35 nm, Vth = 0.8 V, L = 2 μm, W = 30 μm (a) Calculate the unit-area gate capacitance Cox(εo = 8.85×10−14 F/cm and εox = 3.9 for SiO2) (b) Calculate the process transconductance parameter kn′ = μnCox (c) Calculate and plot ID versus VDS for 0 ≤ VDS ≤ 5 V and VGS = 0, 1, 2, 3, 4, and 5 V, respectively. Indicate on each curve the VDS( sat) point the corresponding ID (sat). . (d) Calculate and plot ID versus VGS for 0 ≤ VGS ≤ 5 V and VDS = 1.2 V. Indicate on the curve the transition points between the cutoff region, saturation region, and linear region. (e) Follow Example 3 in the PSPICE simulation tutorial and use PSPICE to simulate the ID−VDS and ID−VGS curves for the MOSFET above. Compare your simulation results with your calculation results in part (c) and (d). Note: In PSPICE, the statement for specifying a MOSFET is: Mname D G S B model_name L = value W = value .Model model_name NMOS(VTO = value KP = value ) where VTO is the threshold voltage Vth, and KP is the process transconductance parameter kn'.
The two CV curves in Fig. 3 are measured on two MOS capacitors of the same area and on the same uniformly doped Si substrate, where VGB is the voltage between gate to substrate. Sample I's gate oxide thickness is Tox1 and Tox2 for Sample II. The dielectric constants of SiO2 and Si are 3.9 and 11.7, respectively. (20%) (a) The measurements are made under high or low frequency? (4%) (b) The Si substrate is n-type or p-type? (4%) (c) If ToxI = 6 nm, what is Tox2(nm)? (4%) (d) For Sample II, what is the expected Cmin ? (4%) (e) At C = Cmin, what is the depletion width into the Si substrate? (4%) Fig. 3
In the given CMOS circuit, VDDP & VDDN are the Supply Voltages. VIN is the Input Voltage. Threshold voltage for NMOS and PMOS transistors are given by Vtn and Vtp respectively. Consider ideal characteristics of transistors. Steady state value of VOUT is V (Note: If result is not an integer, round off to 2 decimal places, Ex: Round off 3.678 to 3.68, 3.671 to 3.67, 3.655 to 3.65)
A differential amplifier is shown below. The MOSFET parameters are listed beside the circuit. N-channel MOSFET parameters Kn = 4×10−5 Vt = 1.5 V VA = 50 V P-channel MOSFET parameters Kp = 4×10.5 Vt = 1.5 V VA = 25 V a) Vsig = 0.01 sin(2π×103 t). What is the output voltage V0(t). b) What is the value of Rref ?
2.12 The full-wave rectifier circuit shown in Figure P2.12 has an input signal whose frequency is 60 Hz. The rms value of vS = 8.5 V. Assume each diode cut-in voltage is Vγ = 0.7 V. (a) What is the maximum value of VO ? (b) If R = 10 Ω, determine the value of C such that the ripple voltage is no larger than 0.25 V. (c) What must be the PIV rating of each diode? Figure P2.12
MOSFET Vth = 1 V, μnCox = 0.4 mA/V2, WL = 20, λ = 0.01 V−1. For a simple calculation of ID, let's assume ID = 1 mA without considering λ. You still use ro for other purposes in this problem. VS = 4.5 V, VD = 7 V, VcC = 15 V, RX = 100 kΩ, RL = 20 kΩ. C1, C2, C3 ≈ ∞ Assume the bias current through R1 and R2 is 2 μA (a) (50 pts) Calculate Rd, Rs, R1, R2, gm, ro (b) (50 pts) Calculate Rint Rout, , Av( = vout vin )
4.19 For the half-wave rectifier circuit in Fig. 4.23(a), show the following: (a) For the half-cycles during which the diode conducts, conduction begins at an angle θ = sin−1(VD/Vs) and terminates at (π−θ), for a total conduction angle of (π − 2θ). (b) The average value (dc component) of vo is Vo ≃ (1/π)Vs − VD/2. (c) The peak diode current is (V1−VD)/R. Find numerical values for these quantities for the case of 12−V (rms) sinusoidal input, VD≃0.7 V, and R = 100 Ω. Also, give the value for PIV. (c) Figure 4.23 (a) Half-wave rectifier. (b) Transfer characteristic of the rectifier circuit. (c) Input and output waveforms.
Problem 5 ( 15 points): Use the Elmore delay approximation to find the worst-case fall delay at output F for the following circuit. The gate sizes of the transistors are shown in the figure. Use the assumption that the diffusion capacitance is equal to the gate capacitance and that a minimum sized transistor has gate and diffusion capacitance equal to C. The resistance of an nMOS transistor with unit width is R. Also assume NO sharing of diffusion regions. Delay =
Consider the following NMOS circuit. a) Calculate the output voltage Vout when Vi = 0 V. b) Calculate the output voltage Vout when Vi = VDDV.
e) The output characteristics of a typical n-channel enhancement type MOSFET are shown in Figure 2 (e). i) Draw this figure in your answer booklet and clearly indicate different regions of 3 operation of the MOSFET on your drawing. ii) Describe the pinch-off voltage, VP, and indicate the approximate position of the 3 pinch-off voltage on one of the curves on your drawing. iii) The drain current in the saturation region is described by the following equation: 4 ID = IDs = μnC0W 2L(VGS−VT)2 = β 2(VGS−VT)2 Describe all terms in this equation. Figure 2 (e).
Q3) Consider a CMOS process for which tox = 6 nm, μn = 460 cm2 /V.s, and VT = 0.5 V. (a) Find Cox and k'. (b) For an NMOS transistor with W/L = 20 μm/0.25 μm, calculate the values of VGS and minimum VDS needed to operate the transistor in the saturation region with ID = 0.5 mA.
Given the availability of NMOS and PMOS transistors that are matched and have kn = kp = 5 mA/V2 and VAn = −VAp = 5 V, design a circuit for an NMOS common-source amplifier with a PMOS currentsource load. Operate each transistor at a dc bias current of 100 μA. What is the output resistance? 100 kΩ 25 kΩ ∞ 50 kΩ
A differential amplifier with a single-ended output is shown below along with the MOSFET parameters. The amplifier is to be designed for a differential mode gain of 10 and a CMRR of 200 . The current source I must have a voltage drop VCS ≥ 1 volt. The voltage V0 = 0 when the MOSFET gates are at ground potential (Va = Vb = 0). Assume the current source I must have a voltage drop of at least Vcs, min = 1 V. MOSFET Parameters kn = 2×10−4 A/V2 Vt = 1 V;VA = 30 V a. Show that the single-ended differential gain can be expressed as Ad = gmro||RD/2 = Ad = kn I VDD(1 + VDD/VA). Hint: Express gm, RD, and ro as functions of the drain current 1 /2. b. Use the result of step #1 to find the required bias current I. c. What should be the value of RD ? d Find the required value of Rss. e. What is the maximum differential input voltage Vid for linear operation. f. What is the common mode input voltage range?
The op amp in the noninverting amplifier circuit below has an input resistance of 400 kΩ, an output resistance of 5 kΩ, and an open-loop gain of 20,000 . Assume that the op amp is operating in its linear region. a) Calculate the voltage gain (vo/vg). b) Find the inverting and noninverting input voltages, vn and vp (in millivolts), if vg = 1 V. c) Calculate the difference (vp − vn) in microvolts when vg = 1 V. d) Repeat a) - c) assuming the op amp is ideal.
Problem 1: The half-wave rectifier in below Figure is operating at a frequency of 60 Hz, and the rms value of the transformer output voltage is 6.3 V. (a) What is the value of the dc output voltage VO if the diode voltage drop is 1 V ? (b) What is the minimum value of C required to maintain the ripple voltage to less than 0.25 V if R = 0.5 Ω ? (c) What is the PIV rating of the diode in this circuit? (d) What is the surge current when power is first applied? (e) What is the amplitude of the repetitive current in the diode?
3.93. The half-wave rectifier in Fig. P3.93 is operating at a frequency of 60 Hz, and the rms value of the transformer output voltage vI is 12.6 V ± 10%. What are the nominal and worst case values of the dc output voltage VO if the diode voltage drop is 1 V ? Figure P3.93
The inverting amplifier in the circuit shown has an input resistance of 400 kΩ, an output resistance of 4 kΩ, and an open-loop gain of 100, 000 . Assume that the amplifier is operating in its linear region. Using the realistic model of the op-amp, calculate the voltage gain (v0/vg) of the amplifier for and R1 = 5 kΩ and R2 = 100 kΩ. In your answer, use point/dot as decimal point. Do NOT use comma. Write your answer with 4 digits to the right of the decimal point. If you find a negative value, don't forget to include a minus sign. (For example, if you calculate the gain as -7.569683, then you should write -7.5697)
The inverting amplifier in the circuit shown has an input resistance of 400 kΩ, an output resistance of 4 kΩ, and an open-loop gain of 150,000 . Assume the amplifier is operating in its linear region. i. Draw the realistic circuit model of the op amp circuit shown above. (2 marks) ii. Calculate the voltage gain (vo/vg) of the amplifier. (5 marks) iii. Determine the resistance seen by the signal source (vg). (3 marks) vi. Repeat (ii) & (iii) assuming an ideal op-amp model. (2 marks)
The op amp in the noninverting amplifier circuit shown below has an input resistance of 400 kΩ, an output resistance of 5 kΩ, and an open-loop gain of 20, 000 . Assume that the op amp is operating in its linear region. If vg = 1 V, find the inverting input voltage, vn, and the noninverting input voltage, vp (in millivolts).
Non-inverting Amplifier The circuit labeled "a" shown in Figure 2 is a non-inverting amplifier. The relationship between the input voltage Vin and the output voltage Vout is Vot = Vin⋅(1 + R2 R1). The gain of this circuit is (1 + R2 R1), which is an ideal circuit for sensors that have high source impedance and thus would be affected by the current draw of the data acquisition system. If R2 = 0 and R1 is removed, then the gain of this non-inverting amplifier is unity. Such a circuit is usually referred to as a follower or a buffer, which can be used to isolate input voltage and output signals. It can serve as protection between the input and output sides. One major advantage of a buffer is that it can boost the current of the input signal to avoid loading effect or distortion for input signals.
For the circuit, suppose β = 50 for the transistor and the input voltage, Vin = 1.5 V. a) What is the base current? Ib = mA b) What is the collector current? Ic = mA c) What is the output voltage? Vout = V
Write down the expression for the minimum value of VDD in terms of Vtn and Vtp (where Vtn > 0 and Vtp < 0 ) that ensures a transmission gate will pass all input voltages between Vin = 0 and Vin = VDD without degradation. Show your steps.
MOSFET amplifier The MOSFET in the circuit below has Vt = 2 V and kn = 1 mA/V2. a) Determine the value of the drain resistor RD that will produce a quiescent point with VOUT = 0 V. Is the MOSFET in saturation? b) What is the amplifier's gain G?
Below is a layout of an NMOS transistor. For the source-to-body junction capacitance Csb without external bias (VS = 0), the value of the sidewall capacitance component was half compared to the bottom plate capacitance component. Find the value of λ in um. Assume CJ = 4 fF/um2 and CJSW = 1 fF/um.
What is the output current /O in the circuit of the given figure if −VEE = −10 V and R = 45 Ω? Assume that the MOSFET is saturated. What is the minimum voltage VDD needed to saturate the MOSFET if VTN = 2.5 V and Kn = 0.25 A/V2. What must be the power dissipation rating of resistor R? (Round the final answer to one decimal place. ) Output current: IO = A Minimum voltage: VDD ≥ V Power dissipation rating: PR = W
For a MOSFET biased in Saturation, plot the following figures under the given conditions. Your plots need not to be accurate but should reflect the actual behavior. Mention the behavior you expect, i. e. "linear", "sqrt", a. gm vs VGS with W/L constant b. gm vs VGS with ID constant c. gm vs ID with W/L constant d. gm vs ID with VGS constant e. gm vs W/L with ID constant f. gm Vs W/L with VGS constant
Q4. (a) Draw the CMOS transistor circuit for X = A + B. (b) A CMOS transistor circuit is shown in Figure 2, find the expression of output X. (c) Implement the logic circuit using NAND gates only for the logic expression X obtained in part (b). (d) Estimate the cost of the circuit obtained in (c). Figure 2