For a differential amplifier shown in Figure 1, assume RI = 5 VT, VT being the thermal voltage. And the maximum magnitude of the input signal ( triangular wave ) is 6.6VT, and the output signal (sine wave) across resistance R has the magnitude value of 2.42VT. Determine the amplitude of the sine-wave output vo, considering RC = 10 kΩ and I = 0.5 mA. Assume α≃1 (a) 5.14 (b) 4.84 (c) 5.00 (d) 4.00
For the circuit given below, C and X are 2 inputs which cause the device to operate in 2 different functions with input C as the selector. Given that I = XQ¯ + CX + C¯X¯Q, when C = 0, the device operates as ; when C = 1, the device operates as Please choose one: a) OT flip-flop; D flip flop
For a circuit with output, W = AQ1¯+A¯BQ2, and flip-flop inputs, D1 = A and ¯D2 = A+B, where A, B are the external inputs, D1 and D2 are the inputs of D flip flops Q1 and Q2 are the outputs of the D flip flops. If T flip-flops are used to replace the D flip-flops, what will be the inputs of T flip flops? Please choose one: a) T1 = A¯Q1+BQ1+AB¯Q1¯, T2 = A¯B¯Q2+BQ2¯ b) 0 T1 = A¯Q1+BQ1+AB¯Q1¯, T2 = A¯B¯Q2+AQ2¯+BQ2¯ c) 0 T1 = A¯+BQ1+AB¯Q1¯, T2 = A¯B¯Q2+AQ2¯+BQ2¯ d) O T T1 = A¯Q1+BQ1+AB¯Q1¯, T2 = A¯Q2+AQ2¯+BQ2¯
Complete the truth table and draw the switching diagram for the following Active high SR flip flop constructed using NOR gate considering the following inputs. (Assume the CLK input is 1 for all the input combinations listed).
Fig. 1. TSPC flip-flop with inverter added. 2) Use logical effort to size the transistors in the TSPC flip-flop shown in Fig. 1. Assume the output load capacitance is 20Cmin . Hint: The 1 st stage of the flip-flop does not affect the clk-to-Q delay. So, you can consider the constant for the first two stages of the flip-flop as 1. The figure below shows the critical path
A JK flip flop logic circuit implementation is given in the figure. Consider this circuit and a. Find the next state table b. Draw the state diagram
The flip-flop in Figure 7-92 is tested under all input conditions as shown. Is it operating properly? If not, what is the most likely fault? (a) (c) (b) (d) Figure 7-92
A D flip-flop can be used at the base component to create other standard flip-flop circuits. For instance, a T flip-flop toggles its output state on the next cycle given its current state. A state table and diagram for a T flip-flop looks like the following, along with T flip-flop circuit implemented using a D flip-flop: T flip-flop Qnext = TQ′+TQ = T⊕Q Use the following state table and diagram to draw the IC for a JK flip-flop that adds a gate onto an SR flip-flop: (2 pts) JK flip-flop Qnext = K′Q+JQ′
Chapter 6, problem 7: For each of the following circuits, complete the timing diagram for the state of each flip flop and the output, where shown. All flip flops are trailing-edge triggered. For those circuits in which there is no clear input, assume each flip flop starts at 0. (a) Chapter 6, problem 8: For the following circuit and input string: Show a timing trace for the flip-flops and the output as far as possible. Assume that the initial value of each flip flop is 0.
The above circuit uses two JK Flip-Flops, each based on a D Flip-Flop as follows: (Scheme 2:) Assuming that the Q value of both JK flip-flops are ' O ' before the clock pulses for the first time (in Scheme 1), and that both flip-flops only update on the rising edge, what are the values of Q1 and Q2 when the clock has pulsed 4 times? Assume that we're checking the values of Q1 and Q2 after enough time has passed after the pulse that if they were going to update, they've updated. Q1: 1, Q2: 1 Q1: 1, Q2: 0 Q1: 0, Q2: 1 Q1: 0, Q2: 0
For the following figure, all the D flip-flops have setup time as 2 ns, hold time as 4 ns, tclk-a-min = 9 ns and tclk-q-m-max = 11 ns. a) Assuming clock period as 25 ns, determine (by using setup equation) if the circuit has setup violation. If there is set up violation, what should be the value of clock period to avoid setup violation. b) Determine (by using hold time equation), if the circuit has hold time violation. [4] c) Modify (and redraw) the circuit without removing any buffers, such that it works at clock period of 25 ns and does not have any timing violations. (Assume only two buffers, with min delay of 6 ns and max delay of 8 ns, are available). Show clear steps/methodology used for arriving at the violation free circuit. [12]
Consider a sequential circuit as shown below. A flip flop with the same timing characteristics is used both the D Flip- Flops above. Which of these Flip flops should we use to maximize the frequency of operation? Note: The flip-flops chosen should meet all the timing constraints in the circuit. FF1 only FF3 only None of these FF2 or FF3 FF2 only
For the D-type positive-edge-triggered flip-flop introduced in Ch. 5.4, shown in Fig. 5.10 in the textbook, reproduced below for your convenience, study the PPT (file name: FlipFlops explanations. ppt) I posted online for Mar 23 to confirm how it works. FIGURE 5.10 D-type positive-edge-triggered Ilip-flop Then answer the following question. What if I replace all the NAND gates in the figure above with NOR gates to obtain a new circuit? Will it still be a flip-flop? Is it positive-edge-triggered? Use the same way that we studied Fig. 5.10 (read your textbook and the slides I posted) to study this new circuit (the one where all NAND gates are replaced with NOR gates).
The flip-flop in Figure 7-92 is tested under all input conditions as shown. Is it operating properly? If not, what is the most likely fault? (a) (c) (b) (d)Determine if the flip-flop in Figure 7-94 is operating properly, and if not, identify the most probable fault.
Obtain the flip-flop output Boolean functions equations on circuit shown in Fig. 1. (Q = D, Q(t+1) = D)Fill in the timing diagram shown in Fig. 2 using the Boolean functions that you obtained. State the task performed by this circuit by using your finding. Figure 1 Figure 2
Flip-Flops and Timing Diagrams (15 points) Complete the timing diagram for the specified flip-flop such that the output Q will be as indicated. Assume that the input signal can change only on the vertical lines. Also, assume that the setup time tsu and the hold time th are each equal to the width of one square. a) Complete the timing diagram for the D input to a negative-edge triggered D flip-flop. b) Complete the timing diagram for the T input to a negative-edge triggered T flip-flop. c) Complete the timing diagram for the J input to a negative-edge triggered JK flip-flop.
B 8-9.* Figure 8-52(a) shows a 74 LS112 J-K flip-flop whose output is required to drive a total of eight standard TTL inputs. Because this exceeds the fan-out of the 74 LS112, a buffer of some type is needed. Figure 8-52(b) shows one possibility using one of the NAND gates from the 74 LS37 (a) (b) FIGURE 8-52 Problems 8-9 and 8-10. quad NAND buffer, which has a much higher fan-out than the 74 LS112. Note that Q¯ is used because the NAND is acting as an INVERTER. Refer to the data sheet for the 74 LS37. (a) Determine its maximum fan-out to standard TTL. (b) Determine its maximum sink current in the LOW state.
(ii) A Master-slave D flip-flop is constructed using two positive D latches as shown in the figure below. The D-to-Q delay (i. e. when the latch is enabled the time taken for output of latch to change after input changes) is 4 ns. The minimum propagation delay and the maximum propagation delay of inverter are given as 1 ns and 2 ns respectively. Determine tsetup , thold , tClk-Qmin and tClk-Qmax for the D flip-flop. Give proper justification* for your answers. [10] (∗Full marks will be given only if there is proper explanation for your Answers)
11.65 The feedback transresistance amplifier in Fig. P11.65 utilizes two identical MOSFETs biased by ideal current sources I = 0.4 mA. The MOSFETs are sized to operate at VOV = 0.2 V and have Vt = 0.5 V and VA = 16 V. The feedback resistance RF = 10 kΩ. (a) If Is has a zero dc component, find the dc voltage at the input, at the drain of Q1, and at the output. (b) Find gm and ro of Q1 and Q2. (c) Provide the A circuit and derive an expression for A in terms of gm1, ro1, gm2, ro2, and RF. (d) What is β ? Give an expression for the loop gain Aβ and the amount of feedback (1+Aβ). (e) Derive an expression for Af. (f) Derive expressions for Ri, Rin , Ro, and Rout . (g) Evaluate A, β, Aβ, Af, Ri, Ro, Rin , and Rout for the component values given. Figure P11.65
10.22 A precision voltage source can be created by driving the drain of a MOSFET. Figure P10.22 shows a circuit that will accomplish this function. With IRef = 0.01 A, determine the output VG. Let K = 0.006 A/V2 and Vt = 1.5 V. Figure P10.22
10.17 The power MOSFET circuit of Figure P10.17 is configured as a voltagecontrolled current source (VCCS). Let K = 1.5 A/V2 and Vt = 3 V. a. If VG = 5 V, find the range of R for which the VCCS will operate. b. If R = 1 Ω, determine the range of VG for which the VCCS will operate. Figure P10.17
Q3. For the amplifier circuit shown, find all the low frequency poles and the low cutoff frequency if gm = 1.25 mS ro2 = 100 kΩ, ro1 → ∞ RD = RG = RL = 10 kΩ C1 = C2 = CS = 10 nF
A negative feedback amplifier is shown below. The small signal equivalent circuit of the open-loop amplifier is shown next to the amplifier schematic. a) Which negative feedback topology is implemented by the amplifier circuit? b) What is the voltage gain Vo/Vsig ? c) What is the input resistance Rin diagrammed in the amplifier schematic?
Below you see an IC MOS amplifier formed by cascading two common source (CS) stages. Assuming that VAn = |VAp| and that the biasing current sources have output resistances equal to those of Q1 and Q2, find an expression for the voltage gain (Av = vo/vi) in terms of gm and ro of Q1 and Q2.
6.1. [12.5 points] Find the complete and detailed steps to express vo in terms of vs in the non-ideal amplifier circuit shown in Figure 4.6.2. [7.5 points] Based on your expression for vo derived in 6.1. , identify the three conditions that characterize an ideal operation amplifier. Note that, under the fulfillment of the three conditions, the expression for vo should reduce to the formula for the ideal inverting operational amplifier introduced in class: vo = −Rf Rs vs. Figure 4. Circuit schematic for Problem 6.
For the given circuit assume the following circuit parameters: gm = 40 mS B = 100 A/A r0 = ∞ Cπ = 18 pF Cμ = 2 pF Assuming: RI = 75 Ω RE = 5 kΩ RC = 3 kΩ R3 = 50 kΩ Find the mid-band voltage gain Amid . Determine all zero and pole locations a low frequencies. Estimate the lower frequency corner wL. Redesign the value of C1 required to set fL(new ) = 400 Hz. Determine all pole locations a high frequencies. Estimate the lower frequency corner wH. Amid = V/V Low Frequencies Z1 = rad/s Z2 = rad/s
PART A: Two-Port Networks An instrumentation amplifier shown in Figure A is an amplifier of low-level signals used in process control or measurement applications and commercially available in single-package units. Show that vo = R2 R1(1 + 2R3 R4)(v2 − v1)
An amplifier circuit is given in the following figure. Design the circuit using the given specifications: λ = 0, VDSQ = 10 V, IDQ = 6 mA, VGSQ = 2.8 V, gm = 2.2 mA/V, Rin = 100 kΩ, RL = 1 kΩ, , and Av = −1. a) Find all the unknown resistors and Kn and VTN values. b) Sketch the small-signal equivalent circuit. c) Derive the small-signal voltage gain Av = vo/vi expression using all the equations obtained from the small-signal equivalent circuit. d) Verify that Av = −1 using the values that you obtained in section (a)
3.1 For the full-wave bridge rectifier shown in Figure 3 below, find the following given that Vin(peak) = 17 V, VD = 0.7 V, R = 200 Ω and rD≪R. (i) Ipeak (ii) Vout (avg) [5] [3] (iii) PIV [2]
MOSFET Vth = 1 V, μnCox = 0.4 mA/V2, W L = 20, λ = 0.01 V−1. For a simple calculation of ID, let's assume ID = 1 mA without considering λ. You still use ro for other purposes in this problem. VS = 4.5 V, VD = 7 V, VCC = 15 V, RX = 100 kΩ, RL = 20 kΩ. C1, C2, C3 ≈ ∞ Assume the bias current through R1 and R2 is 2 μA (a) (50 pts) Calculate Rd, Rs, R1, R2, gm, r0 (b) (50 pts) Calculate Rint Rout, , Av( = vout vin)
Following figure shows a full-wave bridge rectifier circuit that is plugged into a home outlet which is 120VRMS (∼170 V peak). Using practical models for the diodes; a) Find the peak value of the secondary voltage, b) Find the peak value of the output voltage on RL: Vp(out) (Peak), c) Calculate the average value of the output voltage: VAVG, d) Calculate the rms value of the output voltage: VRMS.
For the following full wave rectifier, the output voltage, v3, is shown along with the voltages at the secondary of the transformer, v1 and v2. Figure P3.108(a) Is this circuit operating correctly? If the circuit is operating correctly, explain why the input and output voltages are appropriate. If the circuit is not operating correctly, explain how that is determined from the given waveforms.
The full-wave rectifier in the figure given below is operating at a frequency of 60 Hz, and the rms value of the transformer output voltage is 18 V. What is the value of the dc output voltage if the diode voltage drop is 1 V? (Round the final answer to one decimal place. Include a minus sign if necessary.) V
Question 6. Half-Wave Rectifier [20 pts] Design a half-wave rectifier circuit, such as below, which can convert a sinusoidal voltage input, Vs = 5 sin(2π100⋅ time ), to an almost constant voltage output. (a) Assuming Von = 0.9 V and R = 100 Ω, calculate C which makes the ripple voltage (Vr) is smaller than 0.1 V. Estimate Vdc, Idc, θc, ΔT, Ipeak , Isurge and PIV of the designed half-wave rectifier. (b) Plot Vs and Vout versus time on the same graph.
Consider the full-wave diode rectifier circuit shown in the figure below. Assuming the input voltage is VAC = 170 sin(120πt) the conduction angle of the diode is 32∘, and the load resistance RL = 500 Ω, and the capacitor CS = 100 μF. We assume that all components are ideal and neglect the voltage drop across the diodes. {For the questions below, please only state the value. No need to include the units in your answers}. (a) Estimate the peak-to-peak ripple voltage in the output voltage VR. [2 marks] (b) The average voltage. [2 marks] (c) The RMS voltage. [2 marks] (d) The form factor. [2 marks] (e) If the ripple voltage across the load resistance RL must not exceed 1 V peak to-peak, calculate the value of smoothing capacitance required. You may assume that the capacitor provides current to the load for each complete cycle of the rectified voltage. [4 marks]
Assume M1-M2 and M3-M4 are matched Assume transistor model as transconductance (gmn) and output resistance (Routn) only (ignore body effect and any parasitic capacitances)Calculate the voltage gain of the amplifier Calculate the input-referred noise of the amplifier
Two identical voltage amplifiers have gains which may vary from 50 to 100 without any significant phase shift and are otherwise ideal. The two amplifiers are to be combined in the negative feedback circuits of Fig. 1 to produce an amplifier with an overall gain of at least 100. Calculate the gain variation for each circuit, and hence select the one with the smallest gain variation for this application. Fig. 1.
Problem 1: For the CE Amp circuit in Figure 1, let |VBE| = 0.7 V, β = 100, R1 = 20 kΩ, R2 = 3.6 kΩ, RL = 1.2 kΩ, RE = 0.22 kΩ. VCC = 12 V. Assume IE = 5 mA. Find the overall voltage gain. Show all steps including redrawing the circuit for small signal analysis, the small signal model, and compute the small signal parameters and the gain. Find the actual IE for the circuit, show steps including any equivalent circuit Figure 1. CE Amplifier Circuit