The transistor in the circuit below has parameters VTN = 0.8 V and Kn = 0.25 mA/V2. Determine the Q-point considering the MOSFET to be in non-saturation. RD is given as 3 k and VDD is 5 V. Select one: IDQ = 1.42 mA ∣ VDSQ = 0.641 V IDQ = 1.42 mA ∣ VDSQ = 0.741 V IDQ = 2.42 mA ∣ VDSQ = 0.741 V IDQ = 1.91 mA ∣ VDSQ = 0.957 V IDQ = 1.42 mA ∣ VDSQ = −0.741 V
For each of the circuits below, determine the mode of operation of the MOSFET. VDD = 1.8 V and |VT| = 0.4 V. Cutoff Linear Saturation Depends on the value of R.
Suppose the common-source stage of the figure below is to provide an output swing from 1 V to 2.5 V. Assume that ( W/L) = 100, RD = 2 kΩ, and there are no short channel effects, λ = 0. Knowing that the oxide capacitance is COX = 3.835⋅10−7 F⋅cm−2. the electron mobility μn = 350 cm2⋅V−1⋅s−1 and that the saturation current is given by ID = 12 μn⋅COX⋅W L(VGS − VTH)2, μn = 350 cm2⋅V−1⋅s−1, calculate the input voltages that yield V out = 1 V and V out = 2.5 V.
For the amplifier circuit below, , given Kp = 2.6 mA/V2 assume λ = 0, Vtp = −1.3 V, Q−point(0.6 mA, 3.5 V), VDC = 10 V, R1 = 250 K ohm, R2 = 267 K ohm, R3 = 7 Kohm, Rsig = 2 kohm. Determine the maximum magnitude in mV of source signal to keep the amplifier in the linear range.
To determine the triode and saturation regions, first: Plot the input/output characteristic of the circuit illustrated In Fig. 2 for 0 < Vin < 2 V. What value of Vin yields a transconductance of (50 Ω)-1 for Q1? Assume 10-16 A, VA = ∞, T = 300 k. Fig. 2
Given a MOS capacitor with n-type substrate and Aluminium (Al) gate with tox = 70 nm Nd = 3e15 cm−3. a. Calculate: i. Cox ii. CFB and VFB, iii. Cmin and VT Obs: all capacitances are per unit area (F/cm2) Use the following constants and parameters: ni at 300 K = 1.451010 cm−3, q = 1.610−19 C, ε0 = 8.8510−14 F.cm−1, εSi = 11.7, εox = 3.9 T = 300 K, φM = 4.1 V, χ = 4.05 V, Eg = 1.1 eV b. Draw a simplified high frequency C−V graph using the points calculated previously. Assign the points in the graph. c. Draw a band diagram and a block charge diagram for i. V > 0 (accumulation) ii. VFB iii. VT Example: d. Calculate how much oxide charge needs to be added near the metal electrode in order to change the VT sign.
Q3) Consider a CMOS process for which tox = 6 nm, μn = 460 cm2/V.s, and VT = 0.5 V. (a) Find Cox and k'. (b) For an NMOS transistor with W/L = 20 μm/0.25 μm, calculate the values of VGS and minimum VDS needed to operate the transistor in the saturation region with ID = 0.5 mA.
To determine the triode and saturation regions, first: Plot the input/output characteristic of the stage shown in Fig. 6 for 0 < Vin < 2.5 V. At what value of Vin do Q1 and Q2 carry equal collector currents? Fig. 6
Multiple peripheral devices P1, P2, …, PN, shown in figure, have access to a common data bit line, whose total capacitance is CLINE = 1 pF. Transmitters (TX) and receivers (RX) non inverting buffers are supplied at VDD = 2 V. Contention must be avoided. Consider the figure as a block diagram functional concept. a) Draw a valid CMOS circuit implementation schematic for the receiver buffer RX. Explain your choice. (2) b) Draw a valid CMOS circuit implementation schematic for the transmitter buffer TX. Explain your choice. (2) c) Which is the static power for the implemented CMOS receiver buffer RX? (1) d) Which is the static power for the implemented CMOS transmitter buffer TX? (1) e) Which is the total dynamic power for all the N transmitter buffers if the average rate for commutations of the line (either high to low or low to high) is 2×109 per second? (2)
The arrangements shown in the figure below are used to measure the equivalent resistance of a diode connected MOSFET, the resistance is given Vx Ix = 1 gm + gmb + r0−1 discuss how the equivalent resistance will change if the bulk terminal is connected to the source terminal instead of ground.
MOSFET Vth = 1 V, μnCox = 0.4 mA/V2, W L = 20, λ = 0.01 V−1. For a simple calculation of ID, let's assume ID = 1 mA without considering λ. You still use ro for other purposes in this problem. VS = 4.5 V, VD = 7 V, VCC = 15 V, RX = 100 kΩ, RL = 20 kΩ. C1, C2, C3≈∞ Assume the bias current through R1 and R2 is 2 μA (a) (50 pts) Calculate R0, R5, R1, R2, gm, r0 (b) (50 pts) Calculate Rint Rout Av( = vout vin )
The circuit diagram below shows a full-wave bridge rectifier, and it includes a filter capacitor. If the circuit is powered by 70 Hz mains, and the load resistor is 2600 Ω, calculate a suitable value for the capacitor. If the peak value of the rectified voltage = 400 volts, determine the ripple voltage. Select one: C = 172 nF; Vripple = 45 volts C = 47 μF; Vripple = 1.3 volts C = 0.62 μF; Vripple = 22 volts C = 2 μF; Vripple = 4.0 volts C = 27 μF; Vripple = 40 volts
Consider the amplifier in figure. The MOS parameters are μnCox′ = 100 μA/V, μpCox′ = 50 μA/V, |VT| = 1 V and r0 = 100 kΩ a) Neglect the finite output impedance of the transistors. Compute the DC operating point of the circuit. List all the small signal parameters of the transistors. b) Explain the circuit behavior and derive the ideal small signal transfer vout/vin . c) Compute the DC loop gain. d) Consider the presence of two parasitic capacitances Cp1 = 1 pF and Cp2 = 1 pF connected at the drain node of M1 and M2, respectively. Compute the phase margin to evaluate the circuit stability. e) Compute the output power spectral density considering only the noise generated by the passive elements of the circuit. f) Compute the output power spectral density considering only the noise generated by the active elements of the circuit.
A full bridge rectifier as show in Fig. 2 with a 10 ohm load resistance is supplied by a 120 VAC source. Use the Matlab to compute the average load voltage and current, the RMS source current, and the average and apparent powers of the source. Compute the diode power dissipation and the efficiency if the forward voltage is 1.7 V. Plot voltage output and voltage diode of circuit shown in Fig. 2. vR(θ) = Vmsinθ, 0 ≤ θ ≤ π. i(θ) = VmRsinθ, 0 ≤ θ ≤ π. Figure 2. A full bridge rectifier
Q.3: A bridge-rectifier circuit with a filter capacitor has RL = 100 ohms. The secondary transformer delivers a sinusoid of 15 V(rms) and has a frequency of 60 Hz. The diodes have VDO = 0.7 V each. Figure 3 (a) What will be the value of the filter capacitor C so that the ripple voltage is limited to below 500 mV peak-to-peak? (b) What is the DC voltage at the output of the system? (c) What is the conduction angle for each diode in the system? Explain with appropriate sketches.
It is required to use a bridge rectifier with transformer as shown to design a dc power supply that provides an average dc output voltage on which a maximum of ±0.9 V ripple is allowed. The rectifier feeds a load of 250 Ω. The rectifier is fed from the line voltage ( 120 Vrms, 60 Hz ) through an ideal transformer with a turns ratio of 10:1 to reduce the voltage amplitude. The diodes available have 0.7−V drop when conducting. What is the required value of the filter capacitor in μF, rounded to one decimal place?
For the bridge rectifier circuit shown in the figure below; a. Given the input to be vs = Vssinθ and assuming the minimum conducting angle to be very small (θ0 = 0); use the constant-voltage-drop diode model (VD) to show that: i. The average (or dc component) of the output voltage is Vo≅ (2/π)Vs − 2VD ii. The peak diode current is (Vs − 2VD)/R b. If vs is given to be 15 V (rms) sinusoid, VD = 0.7 V, and R = 150 Ω. Find: i. The numerical values for the quantities defined in part (a) of the question. ii. The PIV (Peak Inverse Voltage) numerical value.
A full-wave bridge rectifier circuit is shown in Fig. 2(a) with a "floating" signal generator and grounded load resistor, which is the most common configuration of this rectifier. Its output waveform appears in Fig. 2 b. Note that the output frequency is twice the input frequency, but the time period T and angular period 2π on the horizontal axis refer to the input waveform. Following a similar development to the halfwave rectifier, the dc output voltage from the full-wave bridge rectifier is given by: Vavg = 1π∫θ1 θ2[Vmsin(θ) − 2Vd]dθ Where, the integration is over half the original waveform's period and the 2Vd term is due to the load current flowing through two diodes. The peak output voltage is vo, peak = Vm − 2Vd. The integration limits are found using Eq. 5 with the angles referred to the original input waveform. θ1 = sin−1(2Vd/Vm) and θ2 = π − θ1 However, the full-wave rectifier's conduction angle must be referred to the output waveform's period, which is half that of the input so φ = 2(θ1−θ2). (a) (b) Fig. 2. (a) Full-wave bridge rectifier circuit and (b) output waveform. Perform the following calculations for the full-wave rectifier in Fig. 2. Put your results in Table 1. a. Determine vo,peak, θ1, and θ2 for the rectifier output waveform of Fig. 2 b. b. Calculate the average (dc) value of vo(t) using Eq. 4 . c. Calculate the conduction angle φ.
For the bridge filter rectifier shown below, the following is given ( AC sinusoidal signal vin with VRMS = 14 V and frequency f = 60 Hz input. For the circuit assume Diode second approximation and a given Load resistance RL = 50 ohm) Develop the equation representing the AC signal and draw it noting the values of both the peak voltage and period. Find the capacitance of the capacitor used within the circuit to generate a ripple voltage Vr of 1.5 V. Find the DC output voltage across the load resistor RL. Draw and note values for the output voltage waveform. Find the Load current. Calculate the PIV across each diode.
If the secondary transformer output voltage v1 in the full wave rectifier circuit below is 14 V: (See the file attached|below) Use a primary voltage of 240 VAC rms. Note that this is idealized in that no resistance is present for either primary or secondary. For the purpose of this problem this simplifies the design, but is not realistic. The full-wave rectifier in Fig. P3.102 is operating at a frequency of 60 Hz, and the rms value of the transformer output voltage is 18 V. (a) What is the value of the de output voltage if the diode voltage drop is 1 V? (b) What is the minimum value of C required to maintain the ripple voltage to less than 0.25 V if R = 0.5 Ω? (c) What is the PIV rating of the diode in this circuit? (d) What is the surge current when power is first applied? (e) What is the amplitude of the repetitive current in the diode?
Full-wave rectifier with R load and C filter is shown in fig.3. The Vs = 250sinωt (V) R = 10 Ω, f = 50 Hz. a. Determine the value of capacitor C so that the Vrip = 10 V. b. Determine (plot) the ON/OFF period of 4 diodes Fig 3
Assume the amplifier is ideal but has finite gain A. M1 and M2 are saturation. Neglect the body effect. Derive an expression for the low frequency output resistance, Rout , in terms of the MOS small signal parameters and A. What is the minimum value of Vref?
A double pulse test circuit, as shown below, has a DC-link voltage, VDC = 100 V and the inductor has a value of L = 200 μH. At t = 0, a gate-source voltage, vgs = 20 V is applied to the MOSFET, which is enough to turn it on. The vgs = 20 V is applied for the time period Ton after which it is turned down to vgs = 0 V for the time period Tof. There is no initial current stored in the inductor prior to t = 0. Describe what is the purpose of the double pulse test circuit, and what information can be derived from the use of the circuit? Explain the purpose of the diode in the double pulse test circuit, and what happens if it is removed? Sketch the currents iL, is and iD as a function of time. Calculate the time Ton required for the inductor current (iL) to be 20 A at the end of t = Ton Calculate how much energy is stored in the inductor L at t = Ton The MOSFET has a thermal resistance junction-to-case, Rsc = 0.8 K/W, case-to-heatsink Rcs = 1.2 K/W and heatsink-toambient RsA = 4 K/W. For a maximum junction temperature of TJ max = 175∘C and ambient temperature TA = 50∘C, what is the maximum allowed power dissipation ?
A full-wave diode bridge rectifier is shown in Fig. 1 . The input voltage is vs = 311×sin(100πt) V. The load resistor R is 10 Ω. ( 25 points) Fig. 1. (a) Sketch the waveforms of the output voltage vd and current id, indicate the peak values. (6 points) (b) Calculate the average value of vd and current id. ( 6 points) (c) If the diodes D1−D4 are replaced by thyristors T1−T4, respectively, to form a controllable rectifier. The firing angle of T1 and T2 and the firing angle of T3 and T4 are both π4. Sketch the waveforms of the output voltage vd and current id, indicate the peak values. (6 points) (d) Based on (c), calculate the average value of vd and current id. (7 points)
(a) ( 12% ) Fill out the missing voltages (indicated with arrows) in the pass transistor circuit below. You may use Vtn (>0) or Vtp (<0) for the NMOS or PMOS threshold voltage if needed. (b) (13%) Pass transistors can be used to build logic gates, also known as pass transistor logic. Are they restoring or non-restoring logic? Identify the logic expressions of U, V, X, Y in the following schematics.
3.1 Consider a device with gm = 7 mmho, Cin = 10.5 pF, Cout = 1.5 pF, and Cf = 0. a If you wanted a fast step response, how many devices would you cascade for a voltage gain magnitude of 400 ? b. If you cascaded three of these devices for a gain magnitude of 1000 , what would you estimate as the minimum rise time for the circuit? c. If we add Cf = 0.5 pF to the device described above we have a circuit for an RCA 40841 MOSFET. What is Elmore's rise time for Vout /VS in the circuit below? ANS: 12, 74.4 ns, 13.5 ns
D *14.8 It is required to design a minimum-area pseudoNMOS inverter with equal high and low noise margins using a 2.5−V supply and devices for which |Vt| = 0.5 V, kn′ = 4 kp′ = 120 μA/V2, and the minimum-size device has (W/L) = 1. Use r = 3.2 and show that NML≃NMH. Specify the values of (W/L)n and (W/L)p. What is the static power dissipated in this gate? What is the ratio of propagation delays for low-to-high and high-to-low transitions? For an equivalent load capacitance of 0.1 pF, find tPLH, tPHL, and tP. At what frequency of operation would the static and dynamic power levels be equal? Is this speed of operation possible in view of the tP value you found?
A NMOS circuit is to be designed as shown in Figure to obtain a current of ID = 100 μA. Calculate the value of VGS KN′ = 200 μA/V2 VTN = 0.6 V, λ = 0 W = 4 μm, L = 0.8 μm 1.55 V 0.55 V 1.05 V 2.15 V
Exercise 1.7 - NMOS Amplifier Uth = 3,8 VK = 1,3 A/V2 a) Calculate the operating point (other word for bias point) of the NMOS circuit. (ID and UDS). b) Simulate the circuit using PSICE or LT-Spice and compare the results concerning the operating point. c) Determine the amplitude of the output signal if we apply an input signal of 100 mV and 1 kHz to the amplifier. d) Are there possibilities to get a higher output amplitude by changing the circuit? What do we need to change or add to the circuit to increase the output signal?
Diode QuestionsIn a power supply, consider the following: A half-wave rectifier, Input voltage is A⋅Sin(ωt) where A = 10 volts, and f = 60 Hz Turn-on voltage of the diode is 0.7 volt, Resistor RL = 100 Ω, Capacitor C = 1000 uF. Approximately Obtain: a) Mean value of the output voltage (Vout, Dropped on RL ). b) Maximum reversed voltage of the diode. c) Maximum variation of the output voltage (ΔV). Assume that RL changes to 500 Ω, recalculate a-c. (a) (b)
Estimate the transient times of the CMOS inverter with the load capacitor, if a transistor (when it is conducting) can be approximated by a resistor of the value Req = 2 μiCox(W/L)i(|VGSi| − |Vti|) where subscript 'i' represents either 'n' or 'p' for an N- and P-MOSFET respectively and Cox = εox/tox⋅( Note: in Spice μi = UO[cm2 /(V⋅s)], and tox = TOX[m]). You can find the values of the transistor parameters in the 0.25 μm CMOS process Wp = 4 μmL = 0.25 μm Wn = 2 μm Figure 2: CMOS inverter
SP. 4. Design problem: Consider a CMOS inverter in 0.8 μm technology with the parameters given in Table 1 . The power supply voltage VDD = 3.3 V. The channel length of both transistors is LN = LP = 0.8 μm. (a) Determine the (Wp/Wn) ratio so that the inverter switching threshold Vth = 1.4 V. (b) The CMOS fabrication process used to manufacture this inverter allows a variation of the Vtn value by ±15% around its nominal value, and a variation of the Kt value by ±20% around its nominal value. Assuming that all other parameters always retain their nominal values, find the upper and lower limits of the switching threshold voltage (Vth) of the inverter in (a). Table 1: MOS transistor parameters
The nMOS transistor in the circuit shown below has a kn = 2 mA/V2 and Vtn = 1 V. a. What is the maximum and minimum VG (gate voltage) for which the transistor operates in the saturation region? b. What is the V0 range for operation in saturation? c. Calculate the drain current ID for VG = 3 V. Hint: Part a. will help you decide the region of operation.
Consider the following ideal voltage transfer curve (Figure 4) for a CMOS inverter. (a) Find VIL, VIH, and Vth for the inverter . (b) Estimate the noise margins for the inverter. Figure 4. Voltage Transfer Characteristics of Inverter
In below circuit, find out the value of Vout. Transistor threshold voltage is Vth = 1 v and vdd = 5 v The Vout will be:
For the circuit below, assume kn′ = 100 uA/V2, and kp′ = 50 uA/V2, Vtn = |Vtp| = 1 V (a) Find the DC drain currents (ID) and verify operating regions of all transistors. (b) Find the small-signal transfer function (vo/vi), for λn = |λp| = 0. (c) Repeat part (b) for λn = |λp| = 0.1 V−1 Simulate the circuits using MULTISIM to verify your results. Provide all necessary plots. Use NMOS transistors for simulation.
Consider the CMOS circuit in the figure, with 3 inputs, A, B and C, and 1 output, out. a) Write the truth table of the circuit. (3) b) Write the Boolean expression for the function implemented by the circuit. (2) c) Indicate the static power dissipation of the circuit. (2) d) Draw a NAND only implementation of the proposed circuit. (1)
An NMOS transistor has a threshold voltage (Vth) of 0.4 V and operates at a supply voltage (Vdd) of 1.2 V. A circuit designer is evaluating a proposal to reduce the threshold voltage Vth by 100 mV to obtain faster transistors. (i) By what factor would the saturation current increase (at Vgs = Vds = VDD ) if the transistors were ideal? (ii) By what factor would the subthreshold leakage current increase at room temperature at Vgs = 0 ? Assume n = 1.3 and vT = 26 mV. (Read Section 2.4.4 of your textbook.)
The MOSFET-based common-source amplifier can be combined with a BJT emitter-follower output stage to construct a circuit that provides voltage gain while taking advantage of the high input impedance of the MOSFET and low output impedance of the emitter follower. For the following, T = 27 C, RD = 5 kΩ, RE = 2 kΩ, VIN, DC = 0.9 V, VDD = 5 V, and CL = 1 uF Use the Analog Devices MAT-02 npn transistor (VA = 150 V, β = 500, IS = 0.6 pA) for your analysis and simulations. Use the Level 1 NMOS SPICE model provided with the assignment (μ = 350, Cox = 384 nF/m2 Vth = 0.7 V, λ = 0.01 V−1, W = 100 μm, L = 1 μm). Analysis a) Estimate the DC operating point of the circuit ( ID0, IC0, V1, DC, and VOUT, DC ) assuming λ = 0 for M1 and VBE = 0.6 V, IB = 0 for Q2.
Given the circuit shown in the figure below, discuss the function of transistor M2 and in what region it will operate in (triode, saturation or cutoff?)
Solve the following problems for a 180 nm 6-layer process having the following measured parameters:Effective output resistance of a unit transistor Ω = 9 kΩGate capacitance of a unit transistor = 7 fF. Relative mobility = 2 Width of a minimum width metal 4 wire = 450 nm. Sheet resistance of metal 4 = 0.03 Ω Let the unit inverter's nMOS transistor have gate width = 3 lambda = 270 nm You may ignore diffusion parasitics. Assume a minimum width wire route of 7 mm in layer 4 metal with Cw = 210 aF/μm. How many repeaters should be inserted for minimum delay? How large should the repeaters be (in terms of multiples of the unit inverter) and what will the delay be once repeaters are inserted?
In a MOSFET, the two-dimensional density of electrons on the surface of a semiconductor is controlled by a voltage applied to a gate that is separated by an insulator from the semiconductor: n = CVg/eA, where C is the capacitance and A is the area of the semiconductor. Consider a MOSFET with area = 10−7 m2 and capacitance = 30 pF = 30×10−12 F in a 0.2 T magnetic field. a) What gate voltage corresponds to filling of one Landau level? b) What is the energy splitting (ΔE) between Landau levels (of the same spin) at this magnetic field? (Assume the effective mass = 0.07 me, the value for GaAs.) What must be the temperature so that there is no thermal excitation into the second Landau level?
9.10. Suppose that in Fig. 9.88, I1 = 100 μA, I2 = 0.5 mA, and (W/L)1−3 = 100 /0.5. Assuming that I1 and I2 are implemented with PMOS devices having (W/L)P = 50 /0.5, (a) Calculate the gate bias voltages of M2 and M3. (b) Determine the maximum allowable output voltage swing. (c) Calculate the overall voltage gain and the input-referred thermal noise voltage.
Assuming the current flowing through R2 is one-tenth of ID1, calculate the values of R1 and R2 so that ID1 = 0.5 mA. μnCox = 200 μA/V2, W/L = 20 /0.18, VTH = 0.4 V, and λ = 0.
17.27 Consider a standard CMOS logic inverter. Let VDD = 1 V, and let a 5-fF capacitance be connected between the output node and ground. Assume there are no other capacitances. If the inverter is switched at the rate of 2.5 GHz, determine the dynamic power dissipation. What is the average current drawn from the dc power supply?
In the circuit shown in Figure 2. f, the transistor is biased in the saturation region. The transistor is an n-channel enhancement type MOSFET with an aspect ratio of (W/L) 15 , a threshold voltage of 2 V, and a gate capacitance per unit area of 480 nF/cm2. The electron mobility is 520 cm2/Vs. The bias parameters are VDD = 5 V, RD = 2.2 kΩ, R1 = 10 MΩ, and R2 = 12 MΩ. Calculate VGS, VDS, and ID at the operating
The MOSFET in the circuit is operated at an overdrive voltage Vov = 2.0 V. RD = RL = 10 kΩ. (1) Determine the value of transconductance gm that would result in an input resistance Rin = 100 Ω. (2) What should the value of the DC current source be in order to satisfy this condition? (3) The DC current source is now selected such that it results in gm = 20 mS. Under this condition, what should the value of the resistance Rsig be in order to result in a voltage gain Av = vo/vsig = 10 V/V?
For the following circuit, n-MOSFET Q1 works as a common source (CS) amplifier while Q2 and Q3 work as a current mirror. These transistors are identical with Vt = 2 V, kn = μnC0 x(W/L) = 2 mA/V2, VA = 100 V, and VDD = VSS = 5 V. (5%) (a) To make sure the resistance of the current mirror is large enough, we would like to have the output resistance (for Q3)r0 = VA/ID = 100 kΩ. Please find the corresponding Rref . (15%) (b) Followed by (a), if the open-circuit gain ( Aw without Rt ) of the CS amplifier is designed to be Avo = −10. What is RD ? What are the corresponding VD and VS for Q1? (5%) (c) Followed by (b), if now the load RL is connected at the drain with a capacitor CL = 100 nF, what is the minimal RL to operate this circuit at low frequency f(L(dB) < 500 Hz. Figure 3
Figure 3.1 shows a mosfet drive circuit for one phase of a unipolar stepper motor where the supply voltage Vs = 12 V; Phase resistance R = 70 R; Phase Inductance L = 60 mH:− (i) How long does it take to establish the rated current of 0.19 Amps in the motor coil once the mosfet switch is turned on? (ii) Explain with the aid of diagrams two methods which can be used to alleviate the L/R time constant limitation of the coil? Figure 3.1 Mosfet drive circuit for one phase of a unipolar stepper motor
A p-channel MOSFET is used in the amplifier circuit shown below. The MOSFET parameters are shown next to the circuit. MOSFET Parameters Vto = 2 VKp = 10−5 A/V2 VA = 30 V a. What is the dc value of V0 ? b. What is the small signal voltage gain vo/vsig ? c. What is the value of Rin ? d. What is the value of Rout?
Calculate the output (junction) capacitance for the following 32 nm CMOS gates. For an NMOS assume: Cj = 25 fF/nm2 and Cisw = 2.6 fF/nm, and for PMOS assume: Cj = 20 fF/nm2 and Cjsw = 2.2 fF/nm. Use LD = 4 nm. Assume minimum length transistors, and no shared diffusion between transistors. a) Inverter: PMOSW = 8 λ, NMOSW = 4 λ b) 2-input NOR: PMOS W = 8 λ, NMOSW = 10 λ
Q2. A) What is the static gate that the following CMOS circuits implement? B) Describe the advantage(s) and disadvantage(s) of configuration #1 compared with #2.
For the MOSFETs (Q1, Q2, Q3 and Q4) in the following circuit ( Figure 3 ), VDD = 6 V, |Vt| = 1 V, λ = 0, μnC2 x = 56 μA/V2, L = (z+1)μm and W = 16 μm. Find V1 and I1. How do these values change if the width of Q1 and Q2 are made to have 10 W ? VDD = 6 V, μnCpx = 83 μA/V2, L = 4 μm, W = 33 μm]
5-) The circuit of Figure below is known as a source-follower configuration. It achieves a DC level shift between the input and output. The value of this shift is determined by the current I0. Assume γ = 0.4, 2|φf| = 0.6 V, VT0 = 0.43 V, k′ = 115 μA/V2, and λ = 0. The NMOS device has W/L = 5.4μ/1.2μ such that the short channel effects are not observed. a. Derive an expression giving Vi as a function of Vo and VT(Vo). If we neglect body effect, what is the nominal value of the level shift performed by this circuit. b. The NMOS transistor experiences a shift in VT due to the body effect. Find VT as a function of Vo for Vo ranging from 0 to 1.5 V with 0.25 V intervals. Plot VT vs. Vo. c. Plot Vo vs. Vi as Vo varies from 0 to 1.5 V with 0.25 V intervals. Plot two curves: one neglecting the body effect and one accounting for it. How does the body effect influence the operation of the level converter? At Vo (body effect) = 1.5 V, find Vo (ideal) and, thus, determine the maximum error introduced by body effect.
Consider the circuit shown below. ISS = 10 μA, VDD = 3 V, VSS = 0 V, VTO = 1 V, kn = 100 μA V2 and λ = 0.2 V−1. Draw the AC and DC equivalent circuits. Assume v1 = VIC + vid 2 and v2 = VIC + −vid 2, each voltage source is a DC + AC signal. Determine the small signal gain vo/vid where vo is the difference between the voltages at the two drains.
The transistors in the below circuit are characterized by |Vt| = 0.5 V, kp = 4 mA/V2, λ = 0. Find the labeled node voltages. Instructions: First, identify the type of transistors. Are they PMOS or NMOS? Next, check whether they are in saturation or in triode mode. We practiced this circuit configuration in class. Then, using the drain current equation, find the unknown node voltages. V1 = 1 V V2 = 2 V
Reverse engineer the schematics & logical expressions from the two layouts below. Here A, B & C are the inputs and X is the output. The color codes for the stick diagrams should be obvious. Layout #1 Layout #2
Derive the expression for the upper cut off frequency, ωH, of a source follower shown below in Fig. 1 using Open Circuit Time constant method. Assume λ ≠ 0. [12] Fig. 1 Fig. 2
a) Size the circuit below for minimal delay from input A to the input of B. The first inverter has an nMOS size of 2/3. Find that value of the minimum delay. (1 pt) b) Draw the full transistor schematic for the 3-input NAND noting the sizes of all the transistors, assuming a 2:1 ratio of the nMOS to pMOS carrier mobility.
Estimate the value of the DC voltage gain (a low frequency AC voltage gain) for the CG stage in Figure 5. The PMOSFET gate length was 1.5 um. The NMOSFET gate length was a half of that for the PMOS device. The NMOSFET aspect ratio was selected to operate the transistors in the saturation region. The NMOSFET gate voltage was found to be 0.8 V. The DC bias current was not given. Assume the NMOS and PMOS devices have the standard process parameters: threshold voltages Vtn = 0.7 V and Vtp = −0.9 V, and the Early voltage parameters Va'n = 20 V/um and Va'p = 10 V/um, respectively. Your Answer: Answer Hide hint for Question 14 The drain current (both DC and AC components) passes through "Rin" into the source terminal and leaves the drain terminal into the PMOSFET which differential resistance rop represents Rload. The output voltage Vout is taken across Rload. The input voltage Vsig is applied across Rin. The voltage gain of the stage Vout/Vin can be found with the ratio Rload/Rin.
Assume VDD = 1.2 volt, Vth1 = 0.2 volt and Vth 2 = −0.3 volt. Determine the maximum value of Vout for which the gain of the diode-connected CS amplifier is 6 . Next, if the gain is increased to 7, then find the maximum value of Vout. Hint: Equation 3.37 on page 56 of the textbook. [Marks 3]
In In the circuit below of Figure Q.12, a MOSFET for which VN = 0.5 V and ka = 0.3 mAV2. Find the value of input voltage V1 so that output voltage Vout = 1.5 V [3 Marks]
An Mosfet has L = 0.4 μm, tox = 8 nm, W = 4 μm, μn = 450 cm2 /Vsec, VT = 0.7 V. Calculate (i) The values of Vgs and VDS min to operate the Mosfet in saturation with a drain current 100 μA. (ii) Find the values of Vgs required to operate a device as 1000 Ω resistor for very small VDS.
Consider the pull-down network below. Assume all the NMOS are in linear region. The equivalent resistance of the NMOS of the left inverter is R (based on linear current equation, i.e. I = β(Vgs− Vt)⋅Vds (ignore the Vds/2 term in ideal model). What is the equivalent resistance from the pulldown network on the right? Ignore body effect. Assume Vdd = 1 V, Vt = 0.45 V, Vout = 0.3 V, A = B = 1 V, and all NMOS has the same size. Hint, equivalent resistance for a transistor in linear region is R = Vds/Ids = 1 /β(Vgs−Vt) (ignore Vds/2 term). You need to find out the voltage level of the node Vmid.
The cascode amplifier is operating at a current 0.1 mA. All the transistors are operating at |Vov| = 0.25 V (absolute value due to PMOS) and all of them have r0 = 40 kΩ. Find the voltage gain Av. If VDD has a value of 1.7 V what can you do to increase the voltage gain. (Find the largest gain that is achievable) Draw the new circuit schematic and find the overall voltage gain. (Hint: To increase the voltage gain you can add transistors in the cascode stack)
For the following two problems, the supply voltage VDD is 3.3 V, and the MOSFET transistors have VTH = 0.5 V, μnCox = 200 μA/V2, and λ = 0. (a) Design this common-source (CS) amplifier with the following constraints. That is, determine the W/L ratio for the MOSFET transistor (M1) and the resistance values for RD, RE, and R2. −RS = 200 Ω and R1 = 100 kΩThe amplifier must provide a small-signal gain ( = vout/vin) of 10. The maximum power budget is 5 mW. At DC, the voltage drop across RE is 0.5 V. The gate overdrive ( = VGS−VTH) of M1 is 0.2 V. (b) Now design this source-follower (SF) stage driving an 8 Ω speaker. RG is 100 kΩ. Determine the W/L ratio of the transistor M2 and the resistance value RS that bias the transistor at gm = 0.15 Ω−1 and ID = 30 mA. Also, calculate the small-signal gain (AVv = vout /vin ) of this SF stage driving the 8 Ω speaker.
A p-channel common source amplifier is shown below. The MOSFET parameters are shown beside the circuit diagram. The amplifier is to be designed to meet to meet the following specifications. Voltage gain = 10; Rin = 1 MΩ; VRD = VRS = VSD = VDD/3 MOSFET Parameters Vto = 1 V kn = 10−5 A/V2 VA = ∞ a) What is the needed drain current IDQ? b) What are the needed values of RS and RD ? c) Determine the values of R1 and R2
Transfer ID−VG characteristic of a MOSFET at 360 K is shown in figure below. (a) What is the subthreshold swing? (4%) (b) Decrease the temperature to 240 K, please plot is ID⋅VG characteristic against the curve below (compare with the one measured at 360 K), what is the subthreshold swing at 240 K? (6%)
Consider the circuit shown. VDD = 2.5 V and I = 0.30 mA. VT = 0.5 V and k′ = 0.1 mA/V2. Given V1 = 2.05 and V2 = 0.8 , determine (W/L)1. Round your answer to one decimal place. Your Answer: Answer
A BJT differential pair is shown as below. All BJTs are assumed to be the same with β = 100 and Early voltage VA = ∞. VCC = 5 V. Please evaluate the following at room temperature (VT = 25 mV) : (10%) (a) If the Rid is designed to be 100 kΩ, what is the current source I needed for the BJT differential pair? What is the biasing voltage at collector (Vc1/Vc2) ? (5%) (b) What is the differential voltage gain (Ad = vod/vid) ? (10%) (c) If we want to design the amplifier with common-mode rejection ratio (CMRR = vod/vid vod/vIcm ) > 1000 (or 60 dB ) for Rc1/Rc2 mismatch = 1% (worst case dRc/Rc = 0.01 ), what is the maximal common-mode gain (Acm) ? What is the minimal resistance for the current source ( Rcurrent source)?
If Vt = 0.7 V, identify the regions of operation of NMOS transistor. Please choose one: a) Saturation region b) Cannot identify c) Cut-off region d) Triode region
Compare and contrast the values of gm, Rin, RO, A0, for a CS amplifier that is designed using an NMOS transistor with L = 0.4 μm and W = 4 μm and fabricated in a 0.25 μm technology specified to have μnC0 x = 267 μA/V2 and VA′ = 10 V/μm, with those for a CE amplifier designed using a BJT fabricated in a process with β = 150 and VA = 40 V. Assume that both devices are operating at a drain (collector) current of 200 μA.
a) Show that C for CMOS inverter can be expressed as C = CN(1 + WP WN)+CW Where CN is determined by the NMOS transistors and the parasitic capacitances is proportional to the width of the relevant transistor. b) Using the equivalent resistances method, find tPHL and tpLH assume (W/L)n = 1, RN,eff = 12.5 kΩ and RP,eff = 30 kΩ for Weff/Leff = 1.
Suppose the common-source stage of the figure below is to provide an output swing from 1 V to 2.5 V. Assume that (W/L) = 100, RD = 2 kΩ, and there are no short channel effects, λ = 0. Knowing that the oxide capacitance is COX = 3.835⋅10−7 F⋅cm−2, the electron mobility μn = 350 cm2⋅V−1⋅s−1 and that the saturation current is given by ID = 12 μn⋅COX⋅WL(VGS − VTH)2, μn = 350 cm2⋅V−1⋅s−1, calculate the input voltages that yield Vout = 1∨ and Vout = 2.5 V. 3.101 V and 5.062 V 0.76 V and 0.81 V 2.333 V and 1.115 V 1.086 V and 0.893 V
a. Find fT for a MOSFET operating at ID = 200 μA and VoV = 0.3 V. The MOSFET has Cgs = 25 fF and Cgd = 5 fF. b. A particular BJT operating at IC = 0.5 mA has Cμ = 1 pF, Cπ = 8 pF, and β = 100. What is fT for this situation? c. A particular small BJT has fT of 10 GHz and Cμ = 0.1 pF when operated at IC = 1.0 mA. What is Cπ in this situation?
For the amplifier shown, Given the following values Find: Ai(mid) = io/ii = The corner frequency of C1 ωc1 = r/s The corner frequency of C2 ωc2 = r/sThe corner frequency of CE ωce = r/s
Calculate the switching power consumed by the static complementary CMOS circuit shown, assuming that all significant capacitances have been lumped into the three capacitors shown in the figure, where CL = 0.2 pF. Assume that VDD = 1.5 V and clock frequency is f = 400 MHz. The distribution of input signals is as follows: PA = 0.3, PB = 0.4, PC = 0.6, PD = 0.5.
Given: A MOSFET is used in a switching power-pole found in Fig. 2-4 a of the text. The operating conditions are as follows: Vin = 35 V, Io = 6 A, the switching frequency fs = 300 kHz, and the duty ratio d = 0.4. a) Consider the diode in the power pole. Assuming an offset voltage forward bias model of the free-wheeling diode in which VFM = 1.2 V, calculate the average forward power loss in the diode. HINT: Consider Eq. 2 A-1. b) In the diode reverse recovery characteristic shown in Fig. 2A−1, ta = 10 ns, trf = 25 ns, and IRRM = 2 A, calculate the average switching power loss in the diode. HINT: Consider Eq. 2 A-2. c) How much in overall average switching loss in MOSFET will be if the impact of diode reverse recovery is included during MOSFET switching? Assume tri = tfi = 20 ns and tfv = trv = 25 ns. d) If the maximum junction temperature of the diode is Tj(max) = 110∘C, what is the maximum acceptable thermal resistance from junction to ambient if the maximum ambient temperature is Ta(max) = 40∘C? Pdiode,F = (1−d)⋅VFMIo Pdiode,sw = (12 IRRMtb)⋅Vd,neg⋅fs
Sketch the output waveforms for the circuits (a) and (b) when a voltage waveform Vs (Figure 1) is applied at the input. Assume that the transistor threshold voltages are 0.8 V and −0.8 V for the NMOS and PMOS transistors respectively, and the time constants are much smaller than the pulse widths. For (b) show both V1 and V2. (In your answer, show both input and output waveforms synchronized) Figure 1. Square waveform (a) An NMOS transistor fed with a Square waveform (i) (ii) (b) Circuits with NMOS and PMOS transistors
Hand calculation. For the hand calculations take VDD = 1.8 V, VnSAT = 1 V VpSAT = 1.83 V Vtn = 0.41 V, Vtp = |−0.43|, Kn = 155 uA/V2, Kp = 72.5 uA/V2, λn = λp = 0.2 V, CL = 10 fF. a) Calculation of W/L of PMOS and NMOS of the combination logic shown in Figure 1. b) Calculate the worst case TPLH and TPHL. c) Calculate the best case TPLH and TPHL. d) Calculate the dynamic power.
This 5 -stage ring oscillator consists of identical inverters whose delays are tpLH = 3 ns and tpHL = 1 ns. What is the period of oscillation P and the high pulse width W of x1 ? Provide your answers as integer numbers. The time scale assumed is nanoseconds.
We would like to design the following circuit such that the worst case propagation delays (tpHL and tpLH ) are limited to 2.14 ns. Use Elmore delay equation to determine the W/L for PMOS and NMOS used in the 2 -input NOR gate. Assume that VDD = 1.2 V, K′n = 90 uA/V2, Vtn = 0.4 V, K′p = 50 uA/V2, and Vtp = −0.5 V in the 100 nm technology node. Also assume that the transistors stay in saturation region for the length of the transition.
Fig. 1 shows the schematic of a circuit in 45 nm technology. Assume μn = 4μp. If (W/L)n = (90/45). Fig. 1 (a) Calculate for the sizes of the following transistors: i. (W/L)p of the PMOS at C ii. (W/L)n of the NMOS at A iii. (W/L)p of the PMOS at B
A 7406 TTL inverter has a maximum tPLH of 15 ns and a tPHL of 23 ns. A positive pulse that lasts 100 ns is applied to the input. (a) Draw the input and output waveforms. Scale the X-axis such that the end time is 200 ns. (b) Label tPLH and tPHL on the graph. (c) What is the pulse width of the output if worst case propagation delays occur?
Assuming that μn = 2μp then a pMOS transistor with three times the channel length and half the channel width of another nMOS transistor produces the same resistance of the nMOS. One-third of the resistance of the nMOS half the resistance of the nMOS 4 times the resistance of the nMOS Twice the resistance of the nMOS One-Sixth of the resistance of the nMOS 3 times the resistance of the nMOS 8 times the resistance of the nMOS
Static CMOS logical family always realize inverted logical functions such as NAND, NOR or A(B+C)¯. This is because Both nMOS and pMOS pass logical 0 and logical 1 voltages levels, respectively, well. nMOS transistors are well-isolate pMOS are good passers of logical 1 pMOS transistors have higher resistance There is a pMOS pull-up (producing the logical 1 output) network, whose transistors that are turned ON with 0 logical input. Also, because there is an nMOS pull-down (producing logical 0 output) network, whose transistors are turned ON with logical 1 inputs.
Assume that in a certain process technology, the mobility of holes in relation to the mobility of electrons, is given by μn = 5 2 μp, then the current capacity of its pMOS transistors is 4 times as the current capacity in its nMOS transistors of the same width/length. the same as the current capacity in its nMOS transistors of the same width/length. 0.4 of the current capacity in its nMOS transistors of the same width/length. 0.8 of the current capacity in its nMOS transistors of the same width/length. twice as the current capacity in its nMOS transistors of the same width/length. 4 times as the current capacity in its nMOS transistors of the same width/length.
Consider an nMOS transistor in a 65 nm process with a minimum drawn channel length of 50 nm(λ = 25 nm). Let W/L = 4/2λ (i.e, 0.1/0.05 μm). In this process, the gate oxide thickness is 10.5 A. Estimate the high-ficld mobility of electrons to be 80 cm2/V⋅s at 70∘C. The threshold voltage is 0.3 V. Plot Ids vs. Vds for Vgs = 0, 0.2, 0.4, 0.6, 0.8, and 1.0 V using the long-channel model. Using MATLAB, plot the I-V characteristics of the transistor. pMOS transistors behave in the same way, but with the signs of all voltages and currents reversed.
For the circuit depicted below, known as a Howland current source, set V2 = 0, R1 = R3, and R2 = R4; then solve for the current /L when R1 = 2R2 = 1 kΩ and RL = 200 Ω. The value of current IL is V1/ A.
MOSFET An enhancement-mode, n-channel MOSFET has a threshold voltage Vt = 1.5 V, transconductance parameter kn = 2 mA/V2, and drain-source voltage VDS = 5 V. a) At what gate-source voltage VGS will the transistor "turn on", that is the channel just forms? b) At what VGS will the device be at the boundary between saturation and the triode region? c) At what VGS will the drain current ID be 2 mA.
The model of an Amplifier is shown below connected to a small signal source Vsig having a series resistance Rsig and to a load resistor RL via coupling capacitors CC1 and CC2 as shown. a) Considering that the magnitude of a capacitor's impedance for sinusoidal sources is ZC = 1/ωC, derive an expression for the magnitude of the voltage gain (Av = Vo/Vsig) as a function of frequency. b) Simplify the expression of part (a) when the source frequency is high and thus the impedances of the capacitors can be considered to be very small. c) Discuss what happens to the gain when the source frequency is low and thus the impedances of the capacitors can be considered to be very high.
The LED in Figure shown requires 30 mA to emit a sufficient level of light. For the following circuit values, determine Rc and the amplitude of the square wave input voltage necessary to make sure that the transistor is in Saturation? [Vcc = 9 V, VCE(sat) = 0.2 V, RB = 3.3 kΩ, βDC = 50, and VLED = 1.8 V]
Consider the circuit shown in Figure 1 where VCC is a fixed voltage. The voltage at the base of the transistor, vB(t), is a time varying waveform described by (1). vB(t) = VB + vb(t) Where VB is a DC offset and vb(t) is a time varying, purely AC signal. Suppose the amplitude of vb(t) is A and we make the following assumptions: The capacitor C is sufficiently large so that it can be considered to be a short circuit at the signal frequencies RC and RE are known R ≫ RC vBE = vBE(sat) β ≫ 1 in the active region vBE(sat) and vCE(sat) are known Figure 1: Circuit for Questions 1 - 3.
Assume the voltage gain is −10, Q1 is in the active mode and the base-collector junction is reverse biased by 200 mV. VCC = 2.5 V, gm = 26−1 Ω−1, IS = 4.3360×10−17 A, VT = 26 mV, β = 100, VA = ∞. (4p) (1) Find RC and RE. (2) Calculate the input and output impedance.
For the common-emitter amplifier shown in Figure 1 , let VCC = 9 V, R1 = 27 kΩ, R2 = 15 kΩ, RE = 1.2 kΩ, and RC = 2.2 kΩ. The transistor has β = 100, VT = 25 mV, VA = ∞ and VBE = 0.7 V. Calculate the DC bias current IE. If the amplifier operates between a source for which RS = 10 kΩ and a load of 2 kΩ, replace the transistor with its hybrid- π model, and find the values of Ri and the voltage gain v0/vs. Figure 1
A lab technician must measure the input resistance Ri of an amplifier. The amplifier has voltage gain Av = vo/vi = 100 V/V. The technician uses the circuit in the figure to perform the task. a) Describe, in the form of an equation, how the technician measures Ri b) The technician measures the resistance to be Ri = 100 kv. If Rx is also 100 kv, how large of a signal generator amplitude vS can the technician use before the amplifier saturates?