Consider the circuit in Fig. 3. (a) Derive the transfer function T(s) = Vo/Vi. [10%] (b) For R1 = R2 = R and C1 = C2 = C, find the quality factor Q of the system based on its transfer function. [10%] (c) For R1 = R2 = R and C1 = C2 = C, find the gain and the phase of the circuit at ω = 1/(RC)⋅[10%] Fig. 3
The circuit in Fig. 4 is a common-source amplifier and the parameters are given as μnCox = 250 μA/V2, VT = 0.6 V and VDD = 1.8 V. It is required that the input DC voltage is 0.8 V. (a) For (W/L)1 = 10, what is the maximum voltage gain available (all transistors are in saturation) and what is the value of (W/L)2? [10%] (b) If the dc power is 90 μW, find (W/L)1 and (W/L)2 to obtain a voltage gain of -2? [10%] Fig. 4
For the differential amplifier in Fig. 3, the parameters are given as R1 = 10 kΩ and R2 = 5 kΩ. Assume all transistors are in saturation with a small-signal transconductance (gm) of 1 mA/V, and the output resistance of the current sources is 10 kΩ. (a)If the devices are matched, find the differential gain (Ad), common-mode gain (Acm) and common-mode rejection ratio (CMRR) of the amplifier. (10%) (b)Assume that the resistance has 1% mismatch. Find the differential gain (Ad), common-mode gain (Acm) and common-mode rejection ratio (CMRR) of the amplifier. (10%) (c)For 1% resistance mismatch, what is required output resistance of the current sources to achieve a CMRR of 140 dB ? (10%)
For the circuit above, find the value of vSD. Assume that the PMOS transistor has Vtp = 1 V and Kp = 0.222 mA/V2
Find the voltages at the base and collector nodes, and the currents in all branches (IB, IE, IC) for the circuit below. Assume β = 75. What's the BJT's mode of operation? a. What if β turned out to be higher by 50%, what would be the operating point, and what would be the BJT's operating mode? Redesign the circuit from problem #2 by choosing a new value for RC that guarantees operation in the active mode for transistors with β ranging between 75 and 200. a. What range of collector voltages would the circuit exhibit over the range of β s?
An op-amp is connected in an inverting configuration with R1 = 2 kΩ and R2 = 150 kΩ. a. Find the closed loop gain, G, for the cases when the open loop gain, A, is equal to 103 and 104. In each case, determine the percentage error in the magnitude of G relative to the ideal value of R2/R1 (obtained if A = ∞). Also determine the voltage that appears at the inverting terminal (v1) when vI = 0.1 V. b. If A drops by 75% from 100, 000 to 25, 000 , what is the corresponding percentage change in the magnitude of the closed loop gain?
Assuming the op amp is ideal, derive an expression for the closed loop gain, G(vO/vI) of the circuit below. Use this circuit to design an inverting amplifier with a gain of 100 and an input resistance of 500 kΩ. Assume that for practical reasons you are limited to resistors less than 1 MΩ.
(a) Show that the overall noise temperature of a system comprised of three 2-port networks connected in cascade as shown in Figure 2 is given by Te = T1 + T2 g1 + T3 g1 g2 Figure 2 (b) Figure 3 shows a cascade connection of cables and amplifiers, where all components are matched to 50 Ω. The input signal Ip is 100 mW. The bandwidth of the system is 10 MHz and the temperature is 290 K. The cables have a loss of 12 dB km−1, and the lengths of cables 1 and 2 are 3 km and 4 km respectively. The amplifiers have gain of 40 dB and a noise figure of 4 dB. Figure 3 Determine: (i) The signal powers at the positions a, b, c and Op. (ii) The signal to noise ratio seen at Op. (iii) The element in the cascade that contributes most to the signal to noise ratio seen at Op.
10.22 A precision voltage source can be created by driving the drain of a MOSFET. Figure P10.22 shows a circuit that will accomplish this function. With IRef = 0.01 A, determine the output VG. Let K = 0.006 A/V2 and Vt = 1.5 V. Figure P10.22
a) Figure Q3 shows an nMOS inverter consisting of a depletion n-channel load (ML) with an enhancement n-channel driver (MD). With the aid of fully labelled and superimposed output characteristics of both devices, briefly describe the operation of the inverter. Figure Q3 b) The inverter in 3a) is to be designed (i. e. find suitable channel widths and channel lengths of MD and ML) to generate an output voltage of 0.2 V for a logic 0 . The supply voltage, VDD is 5 V, the threshold voltages of the load and driver transistors are −2 V and 1 V respectively. Prove any assumptions made. c) Sketch a possible layout of your design in 3b), assuming both the minimum feature size λm and maximum alignment accuracy λa to be 0.5 μm. Make sure to include the alignment error and utilise minimal area. d) Assume the device constant of ML is 1.8×10−4 A/V, calculate the maximum d. c. power dissipation of the inverter.
Using logical effort method, determine the size of each transistor used in this circuit. Suppose the load has 20 fF of capacitance and the inverter has 10 fF of gate capacitance.
Consider the NMOS pass transistor circuit shown in Fig. 3 with VDD = 5 V, Vtn = 1 V, and effective resistance of the transistor Rn = 3 kΩ. Assume that Vour = 0 V at t = 0. Sketch the input and output waveforms when a step input VIN (0 V to VDD) is fed at t = 0. What will be the steady state voltage Vour for t = ∞ ? Figure 3. An NMOS Pass Transistor
a) Draw the schematic of this layout in Figure 3 and write down the data stored in each word line. b) Given VDD = 3 V, VTn = 0.5 V. All the transistors are designed to choose smallest sizes. Body effect and channel length modulation effect are ignored. How to choose Vb to allow the bit line to reach 1 V if the read time is long enough? Figure 3
Consider a resistive-load inverter with the simplified Voltage Transfer Characteristic (VTC) illustrated below. The small signal equivalent circuit analysis reveals a slope |Av| = 3. What is the value of the input low voltage VIL?
In the circuit below, the operational amplifier, ideal for the rest, has saturation levels L+ = −L− = 8 V, C = 1 nF, V1 = −4.3 V, and V2 = 2 V. The voltage across the capacitor is 0 at t = 0. For i(t) = A⋅step(t), with A = 100 μA, a) plot v+(t) and find the value of v+(10 μs) and v+(100 μs), b) plot vo(t) and find the value of vo(10 μs) and vo(100 μs). In case i(t) is a zero average rectangular signal starting at t = 0, with a period T = 100 μs, an amplitude of 100 μA and a duty cycle of 50% c) plot v+(t) for 0 ≤ t ≤ 200 μs, (1) d) plot vo(t) for 0 ≤ t ≤ 200 μs. (1)
For the circuits below, draw the equivalent circuit diagrams where the only components are resistors, voltage sources and current sources. The MOSFET is in saturated mode and the BJT is in active mode. Then use node voltage analysis to solve the current flowing through the 2 kΩ resistor. Use supernode method if "advanced" node analysis method needed. BJT parameters are VBE = 0.7 V and β = 200 MOSFET is to be modelded by a voltage-dependent current source with drain current ID = 0.001vGS
For the circuit, given VDD = 12 V, R1 = R2 = 300 K ohm, and the transistor with Kn = 1.3 mA/V2 and V t n = 2.0 V. Assume λ = 0, determine RD in Kohm so the Q-point is ( 2.0 mA, 2.9 V ).
a. For the amplifier shown below, if RG1 = 2 MΩ, RG2 = 1 MΩ, and Rsig = 200 kΩ, find the value of the coupling capacitor CC1 that places the associated pole at 10 Hz or lower. b. For the same amplifier below, if RD = 10 kΩ, RL = 10 kΩ, and r0 is very large, find the value of CC2 that places the associated pole at 10 Hz or lower. c. If the same amplifier below is biased to operate at gm = 5 mA/V, and RS = 1.8 kΩ. Find the value of CS that places its associated pole at 100 Hz or lower.
Figure 3 shows a differential amplifier circuit. The input common mode level is VCM,in = 0.9 V 'dur. Other parameters are μnCox = 100 μA/V2, λ = 0, VDD = 1.8 V, VTH = 0.4 V. W/L = 50 /0.18, RD = 1 kΩ. 10) The drive voltage in equilibrium (VGS−Vth) = 130.8 mV should be designed as such. What is the required Iss value? a) 0.475 mA b) 0.948 mA c) 0.694 mA d) 0.347 mA e) 1.388 mA 11) What is the maximum RD value that can be connected to keep the transistors in saturation? a) 2.742 kΩ b) 5.474 kΩ c) 3.746 kΩ d) 7.492 kΩ e) 1.873 kΩ 12) Determine the Vin1−Vin2 value that will ensure ID1−ID2 = Iss a) 0.316 V b) 0.158 V c) 0.223 V d) 0.261 V e) 0.185 V13) What is the maximum permissible input common mode voltage level? a) 2.027 V b) 1.962 V c) 1.726 V d) 1.506 V e) 1.853 V 14) Calculate the voltage gain of the differential amplifier. a) 10.68 b) 2.67 c) 3.63 d) 7.29 e) 5.13
CMOS Circuit Analysis a. Find the voltage at points VA, VB, VC of Fig. 3 & Fig. 4 CMOS gate network. (1 Point) Assume threshold voltage (Vt) = 1 V Fig. 3 GND b. Draw the truth table diagram of Eq. 1 (1 Point) c. Draw the transistor diagram of Eq. 1 (1 Point) d. Find out the width of each transistor of Eq. 1 (1 Point) (Assume this function is equivalent of an INV with Wpp = 400 nm;Wn = 200 nm ) e. In general, what gate is better to use to build a circuit if you have a choice of NAND or NOR gates. Write down at least 3 reasons. (1 Point) O = ABC+D¯ Eq. 1
You are asked to design an NMOS inverter with a resistive load, as shown in Figure 2.e, with the input voltage of either 0 V (logic level 0) or 3.3 V (logic level 1). The transistor is an n-channel enhancement type MOSFET with a threshold voltage of VT = 1.5 V, an aspect ratio (W/L) of 20 , and a gate capacitor per unit area of 400 nF/cm2. The electron mobility is 500 cm2 /Vs. When the input is at logic level 1 (vi = 3.3 V), the transistor is in the linear region. Find the values of VDD and RD to have the output voltage of 0.3 V at logic level 0 and 3.3 V at logic level 1. Figure 2. e.
P1. [required assignment] For the Darlington network shown : a. Determine the dc levels of VB1, VC1, VE2, VCB1, and VCE2. b. Find the currents IB1, IB2, and IE2. c. Calculate Zi and Zo. d. Determine the voltage gain Av = Vo/Vi and current gain Ai = Io/Ii. Selected answers: Av = 1 Ai = 2640
A TTL inverter prototype is shown in Figure 8 with the following values: VCC = 3 V, RB = 8 kΩ, and RC = 4 kΩ (12 points) Figure 8 . (a) When Vi = 0.15 V, Q2 is off and Q1 is in saturation with VBEssat = 0.75 V and VCEsat = 0.05 V. Calculate the available currents and the power dissipated in the circuit. (b) When vi = VccQ1 is at reversed active mode with βR = 0.25 and Q2 is in saturation mode with VBEsat = 0.75 V and VCEsat = 0.15 V. Calculate all the available currents and the total power of dissipation.
The iphone- 11 has the capacitance C = 2 nF, and the source current IDD = 9 mA. When VDD = 0.8 V, the iphone -11 can be operated at 1 GHz. When we reduce VDD to 0.6 V, the iphone-11 can work only at 800 MHz. What is the power consumption of iphone-11 working at 1 GHz ? What is the power consumption of iphone-11 running at 800 MHz?
Calculate the drain current of M1 (a) without considering channel-length modulation, (b) including channel-length modulation. Assume μnCox = 200 μA/V2, W/L = 10 /0.18, and VTH = 0.4 V, λ = 0.1 V−1.
SP. 4. Design problem: Consider a CMOS inverter in 0.8 μm technology with the parameters given in Table 1 . The power supply voltage VDD = 3.3 V. The channel length of both transistors is LN = LP = 0.8 μm. (a) Determine the (WP/Wn) ratio so that the inverter switching threshold Vth = 1.4 V. (b) The CMOS fabrication process used to manufacture this inverter allows a variation of the Vtn value by ±15% around its nominal value, and a variation of the Vto value by ±20% around its nominal value. Assuming that all other parameters always retain their nominal values, find the upper and lower limits of the switching threshold voltage ( Vth ) of the inverter in (a). Table 1: MOS transistor parameters
Draw the transistor-level schematic for the CMOS implementation of the following, and state the width of each transistor (in λ s) so that the pull-up and pull-down networks are balanced, assuming that an NMOS transistor is twice as fast as a PMOS (remember a minimum width would be 2λ, the speed scales proportionally to W (remember Req also scales the same way), and series and parallel transistors affect speed differently): a) 4-Input NOR gate b) Three Inverters in Serries
Q1) For the TTL inverter given below a) Find RC/RD ratio using the given voltage transfer characteristic. b) Find RC/RB ratio NoH,max is 10 with 0.6 V high noise margin. c) Find NoL,max. d) Average power dissipation of the given TTL is 5.05 mW when ten similar gates are connected, find RB, RC, and RD.
Consider the inverter connected as shown and with the following characteristics. The n-channel device has a channel length of 50 nm, a channel width of 100 nm, an oxide thickness of 35Å, and an electron mobility of μ = 100 cm2/V⋅s. What is the β (Beta) for this n-channel transistor? The p-channel device has a channel length of 50 nm, a channel width of 200 nm, an oxide thickness of 35Å, and a mobility of μ = 33 cm2/V⋅s. What is the β (Beta) for this p-channel transistor? The transistor thresholds are: Vthn = 0.2 V, and V thp = −0.25 V. The circuit is at the operating point of Vdd = 1.2 V, Vin = 0.5 V, and Vout = 0.6 V. The n-channel transistor is in which of the three operating regions? What is the drain to source current (Ids) for the n-channel transistor? The p-channel transistor is in which of the three operating regions? What is the drain to source current (Ids) for the p-channel transistor? What is the net current from the inverter into the capacitor?
16.17 The voltage-transfer characteristic of a particular logic inverter is modeled by three straight-line segments in the manner shown in Fig. 16.13. If VIL = 1.1 V, VIH = 1.2 V, VOL = 0.3 V, and VOH = 1.5 V, find: (a) the noise margins (b) the value of VM (c) the voltage gain in the transition region Figure 16.13 Voltage-transfer characteristic of an inverter. The VTC is approximated by three straight-line segments. Note the four parameters of the VTC (VOH, VOL, VIL, and VIH) and their use in determining the noise margins (NMH and NML).
Implement a CMOS inverter (circuit shown below) in HSPICE using 20 hp PTM-MG models. Simulate its DC and transient characteristics to obtain the following - a. VOUT vs VIN (voltage transfer characteristics) [Use DC simulation in HSPICE] b. V VOUT vs time, VIN vs time [Use transient simulation in HSPICE] Assume, VDD = 0.9 V. Number of Fins = 2 for all transistors.
Consider an inverter whose input in connected to a clock source with variable input frequency. Suppose you have measured the total power dissipated by the inverter and plotted it as a function of the frequency of the clock source (shown below). You also know that the switching time over which short circuit current flows is 1 ps and the peak short circuit current is 10 uA. From this information, determine the total capacitance at the output of the inverter (CL) and the leakage current of the inverter. Assume VDD = 1 V.
(A) Design a CMOS inverter in LTSpice environment with VDD = 1.8 V. (B) Consider the pull-down network (PDN) given as follows:Calculate the logic function of the given circuit topology. Implement the pull-up network (PUN) of the function. Size the transistors so the gate will operate similar to an optimized inverter with β = 2.
In the active region, the output voltage v0 of the n-channel MOSFET (NMOS) circuit, and the drain current iD, satisfy the relationship vo = VDD − RDiD, where VDD is the unknown battery voltage, and RD is the unknown drain resistance. The values of the output voltage for two different values of the drain current iD are given in the table. Note: There is no expectation that you understand anything about how this circuit works - but you should be able to recognize the parts within this problem that resemble what we've seen in class. (a) Calculate the slope (m) and y-intercept (b) of this line. (b) Graph the output voltage vo as a function of the input drain current iD. On the graph, clearly indicate the slope and y-intercept and their values. (c) Determine the values for the physical properties RD and VDD.
Consider an n-channel MOSFET with tox = 9 nm, μn = 500 cm2/V⋅s, Vtn = 0.7 V, and W/L = 10. Find the drain current in the following cases: (a) vGS = 5 V and vDS = 1 V (b) vGS = 2 V and vDS = 1.3 V (c) vGS = 5 V and vDS = 0.2 V (d) vGS = vDS = 5 V
The sinusoidal voltage source in the circuit shown in (Figure 1) is generating the voltage vg = 1.2 cos100 tV. The op amp is ideal. Write the steady-state expression for vo(t) as vo(t) = Vocos(ωt+ϕ), where −180∘ < ϕ ≤ 180∘.
4.59 In Example 4-9, we analyzed a common-source amplifier without a load resistance. Consider the amplifier in Fig. P4.59; it is identical to the circuit in Fig. 4-31, except that we have added a load resistor RL. Obtain an expression for vout as a function of vs. Figure P4.59: MOSFET circuit for Problem 4.59.
The figure below shows a transistor logic circuit constructed with two NMOS transistors and a 10 kΩ pull-up resistor. For this problem, assume that the effective resistance between drain and source is approximately 0 Ω for the ON state and an open circuit for the OFF state. 1.1 Copy this truth table to your answer sheet and fill it in. Calculate the value for Vout and indicate the state of each of the transistors (ON or OFF) for each of the following input combinations. All voltages are referenced to GND. 1.2 What logic gate does this circuit implement? 1.3 What is the power this logic circuit consumes when Vout = 0 V?
Consider the CMOS transistor logic circuit shown below. 2.1 Copy this truth table to your answer sheet and fill it in. Please enter the output state in the truth table (0 or 1) and indicate the state of transistors PT3 and NT3 (ON or OFF) for each row of the table. 2.2 What logic gate does this circuit represent?
Implement the logic function F = (A+B)C+D+E¯ in complementary CMOS logic using minimum number of transistors as one complex static gate. It is also given that input C changes the most and input E changes the least. Size the devices so the output resistance is the same as that of a CMOS inverter whose device sizing was done so that the PMOS and NMOS aspect ratio match to have the same tpHL and tpLH For the MOSFETs the device parameters kn′ = 90 μA/V2 and kpp′ = 30 μA/V2
Fill in the truth table for the circuit above. It's easy to do. When the input to an NMOS transistor is 1 , the transistor turns on. Therefore, in the circuit above, when C is a 1, the output, F, will be zero. Now you can fill that in on the truth table; whenever C is a 1, F will be 0 . You should also see that when A is 1 and B is 0, the output, F, will be 0, because both series NMOS transistors are on. The PMOS transistor are in the pull-up network. They turn on when their input is 0. If you carefully check every input case, you will see the when the pull-up network is on, the pull-down network is off, and vice-versa. That is a requirement for proper CMOS design. Use the reasoning described above to complete the entire truth table.
The width of the PMOS transistor of a reference CMOS inverter is 2 and the corresponding NMOS is 1. In order for the pull-up resistance to be equal to that of a reference CMOS inverter, the size of the PMOS transistor in this logic gate should be?
Consider the noninverting amplifier circuit shown in Fig. 5. As shown, the circuit is designed for a nominal gain (1 + R2/R1) = 10 V/V. It is fed with a low-frequency sine-wave signal of peak voltage V p and is connected to a load resistor RL. The op amp is specified to have output saturation voltages of ±13 V and output current limits of ±20 mA. a. For Vp = 1 V and RL = 1 k, specify the signal resulting at the output of the amplifier. b. For Vp = 1.5 V and RL = 1 k, specify the signal resulting at the output of the amplifier. c. For RL = 1 k, what is the maximum value of Vp for which an undistorted sine-wave output is obtained? d. For Vp = 1 V, what is the lowest value of RL for which an undistorted sine-wave output is obtained? 5 (a)
The system shown has a closed loop gain of 200. Find the feedback factor β Select one: a. -0.0041 b. -0.0051 c. -0.051 d. -0.041
Figure 1 shows a common-source amplifier circuit with load Resistor as current source. Assume that the transistor has a bias overdrive voltage of 0.3 V, a bias current of 69 μA and the Kn = 300 A/V2. Also assume that the channel-length modulation for the transistor can be neglected. (a) Sketch the small-signal equivalent circuit for the common-source amplifier in Figure 1. (2 marks) (b) Analyse the bias value of the output voltage. (2 marks) (c) Determine the small-signal gain. (3 marks) (d) Design the W/L of the NMOS transistor so that it fulfil the above requirements. (3 marks)
The circuit shown below includes a device known as op amp. This device has two unusual properties in the circuit shown: (1) Vd = 0 V, and (2) no current can flow into either input terminal (marked "-" and " + " inside the symbol), but it can flow through the output terminal (marked "OUT"). This seemingly impossible situation - in direct conflict with KCL- is a result of power leads to the device that are not included in the symbol. Based on this information, calculate Vout. (HINT: two KVL equations are required, both involving the 5 V source.)
Question 21 1 pts Figure 1 Inverter 1, having Cin = 2 pF and Req = 10 kOhms is to drive an external load capacitance, CL = 54 pF. To improve the propagation delay, Inverter 2 and Inverter 3 are to be inserted between the Inverter 1 and the load (Figure 1). Assuming that Inverters 2 and 3 have not been inserted yet, and Inverter 1 is directly driving the load CL, determine the propagation delay tp, in nano-seconds. Round to the nearest tenth. Question 22 1 pts As described in Question 21 above, now Inverters 2 and 3 are inserted. Size the Inverters 2 and 3 for optimal delay. Determine Cin of Inverter 2 in pF. Round to the nearest tenth.
Consider the amplifier circuit in Fig. 4. Assume the channel-length modulation effect of Q1 and Q2 is negligible. (a) Assume all transistor operate in the saturation region. Which action(s) below would cause the voltage gain vo/vi to increase? (i) Increase VG1 (ii) Increase VG2 (iii) Increase RD? Please explain your answer clearly. (9%) (b) Which action(s) below could cause Q1 to leave saturation operation (i. e. entering triode operation) (i) Increase VG1 (ii) Reduce VG2 (iii) Reduce RD ? Please explain your answer clearly. (9%) (c) If Q2 is found to operate in triode region, please suggest how each parameter below should be adjusted (increased or decreased) to bias Q2 in saturation region again? (i) VG1 (ii) VG2 (iii) RD. Please explain your answer clearly. (9%) Figure 4
The input of a voltage amplifier is connected to a 1−kΩ resistor and the output to a 100 kΩ resistor, as shown in Fig. P-4.7.4. The voltage gain of the amplifier is 10, the input impedance is 1 MΩ (assumed noise-free), and the output impedance is 100 Ω (noise-free). The bandwidth of the amplifier is 1 MHz and the amplifier noise is 10 μV rms, referred to the input. The temperature of the entire system is 300 K. Compute the rms thermal noise at the output (point 2). Figure P−4.7.4.
For the MOSFET shown in the figure the threshold voltage |Vtp| = 2 V and βp = 0.2 mA/V2. Assuming that both the transistors are in saturation, determine the value of ID. Hint: Find the voltage at X to determine the VGS of M1.
Task 4 Digital Circuits Fig. 4.1 Fig. 4.2 Given are the CMOS gates according to Fig. 4.1 und Fig. 4.2. a) For the gate from Fig. 4.1 determine the output logic values of Y for all possible input logic values A, B, and C and enter them into a truth table. For some logic states you will not be able to determine the output logic value. Denote these states with Y = Z and explain why a definite value for Y cannot be given. b) Now consider the circuit in Fig. 4.2. Determine the output logic values of Y for all possible input logic values A, B, C, and D and enter them into a truth table. c) Draw the circuit diagram of a level-sensitive D-latch and an edge-triggered master-slave Dflipflop. Given is a sequential circuit according to Fig. 4.3. The edge-triggered registers exhibit the following specifications: setup-time tsetup = 200 ps, hold-time thold = 100 ps, propagation delay tpcq = 50 ps, and contamination delay tccq = 50 ps. The maximum clock frequency is 1 GHz. Fig. 4.3 d) Determine the minimal contamination delay tcd for the combinational logic. e) Determine the maximum propagation delay tpd for the combinational logic.
v1(t) and v2(t) represent two sensors with internal resistance of 1 kΩ each, as shown in the circuit bellow. Also, consider both Op-Amps are ideal. Find the expression of the output voltage vO2(t) in terms of v1(t) and v2(t).
The amplifier shown below uses an ideal Op-Amp. Find the output voltage (vo) as a function of the input voltages (vx, vy):
Consider the PLL shown below. Assume that the relationship between control voltage and output frequency of the VCO is 10 MHz per volt and the op-amp is ideal (a) Find the loop transfer function L(s). (b) Assume VDD = 5 V, R1 = 100 Ω and R2 = 0. What value of C gives a loop crossover frequency of 100 kHz ? What is the phase margin? (c) With the value of C from part (b), find the value of R2 that will provide a phase margin of 45∘ while preserving the crossover frequency.
The transistor parameters: VTP = −1 V, kp = 2 mA/v2, λ = 0 and by using Table 2 . a) Find VSGQ and VSDQ of the FET amplifier as shown In Figure 2. b) Derive an expression for mid-band voltage gain (vo/vs) of the FET amplifier. c) Sketch the gain (vo/vs) in dB versus frequency. Clearly label all break points. Note 1: When designing the circuit, please show the solution step by step. Note 2: The values of all results must be four digits after the point. Figure 2. Table 2
Estimate the maximum allowed output voltage for the p-MOS current source when the current value and the differential output resistance remain nearly constant, e. g. the mosfet operates in the saturation region. The MOSFET is biased with the gate-to-source voltage 1.26 V (absolute value). The current source is powered from the DC voltage source VDD = +3 V. Assume the standard process parameters: Vtp = −0.8 V.
If the inputs to a TTL 3-input NAND gate are (A = LOW, B = HIGH, C = HIGH), then the ON-OFF conditions of each transistor (Q1, Q2, Q3, Q4) in the circuit are: Q1−ON, Q2−OFF, Q3−ON, Q4− OFF Select one: True False
Consider the difference amplifier. In the class, we learned that if R2/R1 = R4/R3, the common mode gain is zero. Now R2/R1 = 100, while R4/R3 = 102. Calculate the common mode gain. Assume the op amp is ideal. Hint: use principle of superposition to calculate Vo1 and Vo2.
a) Determine the center frequency, maximum gain, and bandwidth for the filter given that R2 = 160 kΩ. Give an evidence to show that the gain is limited by another parameter in the circuit. b) Suppose a signal with a maximum voltage of 1 V and a minimum voltage of 100 mV is applied to a transistor-based log amplifier. What will be the maximum and minimum output voltages? What conclusion can you draw from this result? Give numerical evidence for your answer. Assume that: R = 80 kΩ and IEBO = 50 nA
Q11: For each transistor in the circuit shown, kn′ = 120 μA/V2. Also for M1, WL = 4 and Vt = 0.4 V, and for M2, WL = 1 and Vt = −0.6 V. a) Determine the input voltage VI such that both M1 and M2 are biased in the saturation region. b) Determine the region of operation of each transistor and the output voltage VO for VI = 0.6 V and VO > 4.6 V (Ans: 0.7 V, M1 saturation and M2 triode V0 = 4.85 V)
a) A square wave oscillator is to be build using 555 timer IC. The value of R1 = 8.6 kΩ (the upper resistor between Pin7 and Pin8) while the value of R2 = 1 kΩ (the lower resistor between Pin6 and Pin7). A 10 kΩ-potentiometer is connected in series with R2. The value of C = 1000 pF. Calculate the minimum and maximum frequency and minimum and maximum duty cycle. Show how you will modify the circuit design for a 50% duty cycle. b) For the following circuit, calculate the internal drain-source resistance of the JFET and the output frequency. Given that: R1 = R2 = 15 kΩ, R4 = 1.5 kΩ. Describe the rule of the transistor in this circuit.
For the circuit below: (a) Determine Avo, Av, and Gv. (b) If you were designing the amplifier in this circuit, would it be better to have Ri big, or small? What about Ro? (c) For this application, should RL be large or small? How about Rsig?
A. Construct a small-signal equivalent circuit that is appropriate for solving the amplifier's voltage gain (vo/vi), input resistance (Rin) and output resistance (Rout). Carefully label the circuit and identify components and device terminals. B. Determine the circuit's small-signal input resistance, Rin (as shown). C. Solve for the circuit's small-signal output resistance, Rout (as shown). D. Determine the amplifier's small-signal voltage gain, Av = vo/vi. MOSFET Parameters: Kn = μnCoxW/L = 0.2 mA/V2 VTN = 1 V λ = 0 Vt = 1 V gm = 1 mA/V χ = 0.2 (body effect)
(a) For the configurations shown below ("diode-connected configuration"), determine the small-signal input resistances Rx and RY. Do not neglect channel-length modulation effect. Also, do not neglect body effect. Note: Small-signal resistance R is defined as v/i in the small-signal model of circuit. (b) Calculate the small-signal gain of the following "Common-Source Amplifiers with Diode-Connected Load" using two methods: 1) replacing transistors with their small signal model 2) replacing the diode-connected Mosfets with their input resistances calculated in (a). (c) What is the benefit of using PMOS diode-connected load over NMOS?
Output voltage Vx of a voltage divider circuit (in location-2 configuration as shown below) in stage-1 signal conditioning has a full measuring range from 1.43 V to 2.73 V which needs to be adjusted to required full measuring range from 0 V to 5 V through linear measuring function Vout = KVx + Vo of stage-2 signal conditioning. (1) Find the slope K and intersect V0 (in volt) of the required linear voltage measuring function for the given required full measuring range. Provide a MATLAB plot for the required linear measuring function. (2) If a differential op-amp circuit is used to implement the required linear voltage measuring function obtained in (1), (a) Provide the schematics of the designed stage-2 differential op-amp circuit and its connection to the given voltage divider circuit in stage-1 signal conditioning. (b) Provide values of resistors that define the circuit's gain as A = R2 R1 (c) Proved the required values of input voltages V2 and V1 of the designed differential opamp circuit.
Given: VDD = 1.8 V, RG = 100 kΩ, RL = 3 kΩ, W/L = 5, VTO = 0.60 V, KP = 250 µA/V2, LAMBDA = 0.20 V-1, VSB = 0 V. Determine the operating drain current of the circuit. ID = mA Please use this formula for Id below since lambda is not equal to zero. You will probably arrive in three equations below, to get the Vgs. Note: Vth is equal to 0.6 V since V sb is equal to zero. V th = VTO Vdd-Vgs-IdRs = 0 Id = Vg−Vgd/Rs Vdd-Vds-IdRs = 0 Vds = Vdd−IdRs
A differential amplifier connected in the circuit in the given figure has the parameters listed below with RI = 6.0 kΩ and RL = 450 Ω: Input resistance Rid = 1.2 MΩ Output resistance RO = 20 Ω A = 40 dB vi = Vlsinωt What is the amplitude VI of the sinusoidal input signal needed to develop a 20−V peak-to-peak signal at vO ? (Round the final answer to one decimal place.) The amplitude VI is = mV
Statement I: In a MOS cascode amplifier, the cascaded transistor is required to increase the output impedance by a factor of 40. If overdrive voltage (Vov = VGS − VTH) of the cascaded transistor is 0.2 V. Then, channel length modulation parameter (λ) is 0.25 V−1. Statement II: If we have K = gm2 ro2 = 40, then λ can be obtained as 1 λ = KVov 2, which results in λ = 0.25 V−1. Both statement I and statement II are true, and statement II is not the correct explanation for statement I. Both the statements are false. Statement I is true, and Statement II is false. Both statement I and statement II are true, and statement II is the correct explanation for statement I.
Transistors Q1 and Q2 in the figure below have emitter-base junction areas in the ratio of 1:4 all other characteristics are identical. Vcc = 5 V. If VBE = 0.6 v, and β = 200 (a) Determine R1 to establish a 600 μA reference current. (b) Calculate the collector current IC1. (c) Calculate the collector current IC2 in Q2? (d) Calculate the collector voltage Vc1 of Q1?
The figure shows the high- frequency capacitance-voltage (C−V) characteristic of a Metal/SiO2/silicon (MOS) capacitor having an area of 1×10−4 cm2. Assume that the permittivities ϵ0ϵr of silicon and SiO2 are 1×1012 F/cm and 3.5×10−13 F/cm respectively. Calculate The gate oxide thickness in the MOS capacitor.
Problem 1 (10 points): A model for the drain current of a MOS transistor with velocity-saturation effect is given by IDSAT = 1 1 + (VGS−Vt)/(EsatL)(μ0COX 2)W L(VGS−Vt)2 Using this equation it is possible to observe the velocity saturation effect modeled by a MOS device with a source-degeneration resistor as shown in Figure 1. a. Find the value of RS such that IDSAT(VGS, VDS) for the composite transistor in the figure matches the above velocity-saturated drain current equation. Hint: the voltage drop across RS is typically small. b. Given Esat = 1.5 V/um and u0Cox = 20 μA/V2, what value of RS is required to model the velocity saturation effect. How does this value depend on W and L? Figure 1. Source-degeneration model of velocity saturation.
Consider an op amp having a single-pole, open-loop response with A0 = 106 and fP = 10 Hz. Let the op amp be ideal otherwise (infinite input impedance, zero output impedance, etc.). (1) If the op amp wired as a unity-gain buffer, how large is β? (2) At what frequency the loop gain Aβ is equal to 1? What is the corresponding phase margin? (3) For the case of a manufacturing error introducing a second pole at 103 Hz. Sketch the bode plot of the open loop gain. What is now the frequency for which |Aβ| = 1? What is the corresponding phase margin? For what values of β is the phase margin 45∘ or more?
The model of a voltage Amplifier is shown below connected to a small signal source vs having a series resistance Rs and to a load resistor RL. a) If the amplifier's input resistance (Ri) is 100 kΩ, what is the range of values that the series resistance Rs can have if we wish 90% or more of the small signal source signal to be coupled into the amplifier. b) If the amplifier's output resistance (Ro) is 2 kΩ What is the range of values that the load resistance RL can have if we wish 90% or more of the amplifier's dependent voltage source voltage to be delivered (i. e. dropped) to the load resistor.
The model of a BJT amplifier circuit connected to a small signal source VS and to a load resistor RL is shown below. Calculate an expression for the small signal gain defined as: Av = Vo/VS
In the following amplifier circuit we know that Rsig is very small and ro is very large. Given that the values of the other resistors are: RB1 = 10 kΩ, RB2 = 10 kΩ, rπ = 5 kΩ, RC = 10 kΩ and RL = 10 kΩ, and that the value of gm = 0.03 (Ω−1), determine the gain of this amplifier defined as: AV = Vo/Vsig
The width of the PMOS transistor of a reference CMOS inverter is 2 and the corresponding NMOS is 1. The sum of the widths of the NMOS transistors of the logic gate shown, so that the worst-case pull-up and pull-down resistance is identical to that of a reference CMOS inverter is
The introduction to basic logic-circuit concepts that apply to MOSFET circuits is the most popular technology for implementation of digital systems. The two families of MOS logic circuits introduce are NMOS and CMOS (a) Given a NMOS inverter with a current source pull-up using the following specification data: μnCox = 50 μA/V2, μpCox = 25 μA/V2 VTn = −VTp = 1 V, VDD = 5 V, Ln = Lp = 1.5 μm λn = λp = 0.1 V−1 Find the width of the device so its saturation current is 200 μA when VB = 3 V. (5 marks) ii. Calculate the required width of the n-channel device so VOUT is 0.05 V when VIN is 5 V. (5 marks) (b) Consider a simple NMOS inverter with a resistor pull-up as shown in Figure 5 using the following specification data. i. Determine the value of pull-up resistor, R for the inverter. (4 marks) ii. Find the required value for fabrication width and length, (W/L). ( 6 marks) μnCox = 100 μA/V2, VTn = −VTp = 1 V V1 = 5 V, VDD = 5 V, VO = 50 mV, rDS = 50 ohm
All the transistors in the circuit shown are matched and are in the active region. Assuming that all the transistors have β = ∞. IE4 = mA VA = V VC = V VD = V
Consider the following differential amplifier. Assume all transistors are operating in saturation region and λ = γ = 0, VDD = 3 V, VTH(NMOS) = 0.5 V, μnCox = 1 mA/V2, R = 100 Ω, (W/L)1 = (W/L)2 = 16 and (W/L)0 = 32. Also, assume that the Vbias = 0.75 V and the circuit is symmetric. a) What should the value of RL be if the magnitude of the differential voltage gain of the circuit is 4 V/V b) For the circuit to operate properly (i. e. , all transistors operate in their saturation region), what are the minimum and maximum values of the input common-mode voltage (i. e. , input DC voltage)
Q1) The parameters of the MOSFET in the circuit shown in the figure are VTN = 0.7 V, Kn = 0.8 mA/V2, and λ = 0.02 V-1. Determine RS and RD such that IDQ = 0.1 mA and VDSQ = 6 V.
Assume: All transistors in saturation region, λ = γ = 0, VDD = 3 V, VTH(NMOS) = 0.5 V, μnCox = 1 mA/V2, R = 100 Ω, (W/L)1 = (W/L)2 = 16 and (W/L)0 = 32. Vbias = 0.75 V 1. Value of RL if differential voltage gain is 4 V/V 2. To operate all transistors to be in saturation region, what is min/max value of input DC voltage?
For the circuit shown below, all transistors operate in the saturation region. a. Assuming that ID1 = ID4, calculate the DC currents of M1 to M5. b. Determine the ac output impedance c. Calculate the ac voltage gain d. Calculate the ac input impedance e. Calculate the maximum voltage swing at the gate node of M4 f. What is the minimum value of VG4 to keep M4 in saturation? g. Maximum amplitude of input ac signal for linear operation of the circuit NMOS current equation in saturation is iD = K(vGS − Vth)2 Ignore channel-length modulation in DC analyses. R1 = 6 KΩ, R2 = 4 KΩ, R3 = 100 Ω, R4 = 0.6 KΩ, VDD = 4 V, VA = 100 V Kn = 1 mA V2, KP = 25 16 mA V2, Vth1 = 0.5 V, Vth2 = 0.4 V, RS = 100 Ω
Consider the circuit in Figure 1. (1) Given that the VTN = 3 V, k = 7 (A/V2), and the RDD = 0 (short circuit). Sketch and clearly labeled the iD−VDS diagram with VG is 2 V, 4 V, 6 V and with the VDS varying in the range from 0∼15 V (in the same diagram). (2) If the gate voltage is 6 V, find the transconductance and the resistance. (3) Find the minimum RDD that make the transistor work in the triode region when VG = 6 V and VDD = 15 V. Figure 1.