Consider the NMOS inverter as shown in Figure 1.1. a) Design the circuit such that the power dissipation is 80 μW and the output voltage is vO = 0.06 V when vI is a logic 1. b) Used the result in part (a), determine the transition points for the driver and load transistor. c) If (W/L)D found in part (a) is doubled, what is the maximum power dissipation in the inverter and what is vO when vI is a logic 1 Figure 1.1
Consider the NMOS inverter with depletion load driven by three NMOS transmission gates in series. Assume threshold voltages of the n-channel transmission gate transistors and the driver transistor are VTN = 0.8 V, and the threshold voltage of the load transistor is VTNL = −1.5 V. Also, assume that kmD = 50 μA/V2, knL = 10 μA/V2 and the length of the channels for Load and Driver is 0.1 μm. Design WDWL such that vO = 0.1 V when vI = VDD, A = B = VDD, and C = VDD−2VTN
Consider the circuit with a depletion load device shown in Figure 1.3. a) For vX = 1.8 V and vY = 0.1 V, determine KD/KL such that vO = 0.1 V. b) Using the results of part (a), determine vO when vX = vY = 1.8 V. c) If (W/L)L = 1, determine the power dissipation in the logic circuit for the input condition listed in parts (a) and (b). Figure 1.3
Consider the circuit in Figure 5.5. Device M1 is a standard NMOS device. Device M2 has all the same properties as M1, except that its device threshold voltage is negative and has a value of −0.4 V. Assume that all the current equations and inequality equations (to determine the mode of operation) for the depletion device M2 are the same as a regular NMOS. Assume that the input IN has a 0 V to 2.5 V swing. a. Device M2 has its gate terminal connected to its source terminal. If VIN = 0 V, what is the output voltage? In steady state, what is the mode of operation of device M2 for this input? b. Compute the output voltage for VIN = 2.5 V. You may assume that VOUT is small to simplify your calculation. In steady state, what is the mode of operation of device M2 for this input? c. Assuming Pr(IN = 0) = 0.3, what is the static power dissipation of this circuit?
Q 3. The depletion NMOS amplifier of Figure 2 has Rs = 500 Ω, RL = 10 kΩ, RSR = RD = 5 kΩ, RG = 100 kΩ, IDD = 10 mA, Vp = −4 V, |VM| = 200 V, and VDD = 12 V. Calculate (a) the input resistance Rin = vs/is, (b) the no-load voltage gain Avo = vo/vg, (c) the output resistance Ro, and (d) the overall voltage gain Av = vL/vs.
Consider the following 3 inputs NOR gate. a) Determine KD KL for which the maximum value of output in its low state is vo = 0.15 V. b) Determine vo when i. vA = 3 V, vB = vC = 0 V ii. vA = vB = 3 V, vC = 0 V iii. vA = vB = vC = 3 V c) Determine power dissipation for each case given in part(b).
For the depletion load inverter shown in Figure below, assume parameters of VDD = 3 V, VTND = 1 V, VTNL = −0.8 V, KD = 500 μA/V2, and KL = 200 μA/V2. (a) Draw the Inverter Transfer Function and indicate its VOH, VOL and VIt (b) Determine the maximum current and maximum power dissipation in the circuit. (c) An Integrated Circuit (IC) composed of 1000 of such an inverter, determine the total static power consumed by this IC.
PROBLEM 2: Depletion load inverter. 20 points VTND = 1 V and VTNL = −1 V a. If v1 = 4.2 V, what approximate value is vo? What is the operation mode for each MOSFET in this case? Show the VDS(sat) calculation. b. If v1 = 0.8 V, what approximate value is vo? What is the operation mode for each MOSFET in this case? Show the VDS(sat) calculation.
Consider the circuit with depletion load device in Figure below, (a) For Vx = 2 V and VY = 0 V, determine KD/KL such that V0 = 0.15 V. (b) Using the result of part (a), determine V0 when Vx = VY = 2 V. (c) If the width-to-length ratio of the depletion load is 1 , determine the power dissipation in the logic circuit for input conditions listed in parts (a) and (b)
An n-channel depletion type MOSFET datasheet gives the values of IDDS = 7 mA and VGS, off = −3.7 V. Determine the drain-source resistance, RDS, when VGS = −3 V. Round your answer to the nearest whole number but do not round to E−12 values.
P R O B LEM II. 6 a) Express F¯ in a simplified sum-of-products form given that F = AB¯+CD¯. b) Implement the logic function F = AB¯+CD¯ with an NMOS digital logic circuit that obeys the static discipline defined by the low-level and high-level logic thresholds VIL = VOL = VL and VIH = VOH = VH, respectively. Assume the supply voltage is VS, and that the on-state resistance of the NMOS transistors is RON. Determine the lowest value of the pull-up resistor RPU for which the circuit will obey the static discipline in terms of RON, VS, VL, and VH; not all variables need appear in your answer. c) Implement the logic function F = AB¯+CD¯ with a CMOS digital logic circuit. (Hint: make use of the result from part (a). ) d) Suppose that the NMOS and CMOS circuits above drive a capacitance CL. Assume that the on-state resistance of both the PMOS and NMOS transistors is RON. For both the NMOS and CMOS circuits determine the worst-case output rise time. For the purpose of this problem, assume that the worst-case output rise time is the time the output takes to go from 0 V to VH. Sketch the form of the output for both the NMOS and the CMOS circuit. e) Suppose that the inputs are arranged such that B = 1, C = 0, and D = 1, and that a 0−V to 5−V square-wave signal is applied to the input A. Assume the square wave cycle time is T, and that T is large enough so that the output comes close to its steady state value for both falling and rising transitions. Under these conditions, compute the power consumed by the CMOS and NMOS circuits when driving the capacitance CL load.
In the following circuit: a) Find the time needed for the output to change from a high state to 0.9 VOH. VDD = 5 V, (W/L)N = 5, (W/L)P = 2.5, LN = LP = 1 μm, kN′ = kP′ = 20 μA/V2, VTN = 1 V, VTP = −1 V, and CL = 1 pF. b) Find the propagation delay time. c) What should you do to reduce this time delay?
In this problem you will choose the number of stages and the sizing for the inverter chain shown in Figure 1. You should assume that the input capacitance of the first inverter is Cu, γ = 1, and tinv is the unit delay of an inverter as defined in lecture (i. e. , tp = tinv(γ + f) Figure 1. a) Given that Cout = 624∗Cu, what is the optimal number of stages to use for this inverter chain? (Note that you don't need to worry about the logical polarity of the signal. ) b) Using your answer to part a), what is the optimal delay of the inverter chain? c) Now let's look at the chain of just two inverters shown in Figure 2, with given Cout, Cu, and R2 = k∗Rinv1 (where Rinv1 is the on resistance of the first inverter). What C2 (input cap of the second inverter) gives the minimum delay? Figure 2.
The following circuit is a common drain amplifier. A small-signal vin is applied to the gate input with a DC bias of V GS. Express the voltage gain A0 using the symbols used in the figure. Here, r0 and gm are the output resistance and the transconductance of the MOSFET, respectively.
Question (6) The Ids versus Vgs curves for a native n-channel silicon MOSFET with fixed Vds = 50 mV are shown in Fig. (5). The transistor has channel length L = 20 μm, channel width W = 100 μm and substrate doping concentration Na = 5×1016 cm−3. Find the threshold voltages at Vbs = −1 V and Vbs = −5 V. Calculate the oxide thickness ToxFind the carrier effective mobility in the channel. (neglect mobility variation with gate voltage)Calculate the flat band voltage of the device. Sketch the high frequency C−Vgs curve when the source, drain and substrate terminals are grounded. Indicate the numerical values of VFB, Vth and Cmin on the graph. (6 Marks) Figure (5)
The figure below shows a S-R latch (Vdd = 2.5 v, L = 0.25 um, λ = 0, γ = 0, neglect short channel effects, (W/L)1,3 = 2, (W/L)2,4 = 8) (a) Find the minimum values of M5, M6, M7 and M8 that will allow the latch to switch states (b) Find the minimum width of the set or reset pulse to ensure proper operation. Assume CQ = 20 fF and Ca = 20 F (c) Modify the circuit above (show the drawing) such that it becomes a SRAM cell. Make sure to label all the devices as well as the relevant signal lines. Find the size for the access device for a write operation. (d) What is the static power dissipation of the memory cell in (c)?
Figure Q5 shows a single-stage amplifier circuit. The device parameters are as follows -n-channel MOSFETs: Kn = 1 mA/V2, VTHN = 1 V and λn = 0.01 V−1. p-channel MOSFETs: Kp = 2.5 mA/V2, VTHP = −1 V, and λp = 0.01 V−1. Fig. Q5 MOSFET M1 is operating in saturation region and its DC drain current is 1 mA. Ignore Channel Length Modulation effect in DC analysis. (a) Determine the DC drain current of M3 and RREF. (b) Determine R2. (c) Identify the amplifier configuration. (d) Determine the small-signal parameters of MOSFET M1:gm,M1, ro, M1 and gmb,M1. (e) Calculate the two-port network parameters of the amplifier: Rin, Rout and Gm (or Av). (f) Estimate the voltage gain vout /vs of the amplifier.
Consider MOSFET-based current source circuits shown below. Assume that the n-type MOSFET transistors follow the long-channel model with μnCox = 100 μA/V2 and Vth,n = 0.5 V. All the transistors have a fixed channel length L = 0.25 μm. The bias voltage VB1 is at 0.8 V. Assume that all transistors have no back-bias effect. (1) (2) (a) For a basic current source in Fig. (1), size the NMOS transistor M1's width ( = W1) so that it conducts a current of 1 mA when it operates in saturation region. You may assume λn = 0. (b) What is the minimum value of Vout for this circuit that keeps M1 in saturation region? (c) For a cascode current source in Fig. (2), assume that the transistor M2 has the same width with M1 you determined from part (a). Determine the value of VB2 that yields the lowest minimum VOUT keeping both M1 and M2 in saturation regions. (d) Now, let's assume that the transistors M1 and M2 have a finite output resistance with λn = 0.1 V−1. Compute the value of the output resistance (Rout) of this cascode current source when M1 and M2 are in the saturation region. (Hint: Calculate the output impedance in a small signal equivalent circuit.)
(50%) Analysis of a MOSFET Amplifier (a) (30%) Small-signal (AC) Analysis: All the capacitances are considered to be infinite. Draw the small-signal model. Determine Avo ( voul /vin), input resistance Rh, and output resistance Ro. (b) (20%) The values of the parameters are given as: VDD = 12 V, RD = 1 kΩ, RP = RG = 100 kΩ, kn′(WL) = 0.01 mA/V2, V1 = 1 V. Determine Vss to make |Avo| = 10 V/V and check the operation mode of the MOSFET. N-channel MOSFETs - DC Analysis
For the CMOS circuit below, complete the truth table. NOTE: For a truth table question, you only get one chance to get each answer correct. Additional tries will result in a penalty each retried portion of the table.
Estimate the maximum allowed output voltage for the p-MOS current source when the current value and the differential output resistance remain nearly constant, e. g. the mosfet operates in the saturation region. The MOSFET is biased with the gate-to-source voltage 1.26 V (absolute value). The current source is powered from the DC voltage source VDD = +3 V. Assume the standard process parameters: Vtp = −0.8 V.
A designer uses a CMOS technology with VDD = 3.3 V. He builds a inverter that has a VOH = 3.3 V but is unable to lower VOL below 0.3 V. Also VIH = 2.5 V and VIL = 1.0 V. a) Draw the VTC for this inverter. b) For this inverter, find the values for the i. logic swing ii. noise margins high and low. c) This inverter drives another similar inverter. i. How much noise can be introduced at the output of the first inverter before the second inverter will fail to d) If the inverter drives a load capacitance of 1 pF, what is the energy dissipated per cycle.
Consider the diode circuit shown in Fig. Q6. Assume VD0 = 0.7 V and the diode breakdown voltage is at 10 V. Fig. Q6 (a) If VI operates between 0 to 9 V and VDD is 9 V, which operating region would both diodes be in? (b) Supposed RI is 10 kΩ, VDD is 1 V, and V1 is now 20 V. Assume Dl is forward biased and D2 is reversed biased. Determine V2 and thus IR1. (c) Explain why in part (b), the diode D2 is not operating in the breakdown region. (d) Supposed R1 is 10 kΩ, VDD is 1 V, and V1 is now −20 V. Assume D2 is forward biased and D1 is reversed biased. Determine V2 and thus IR1.
For Fig. 2: e. Is this an NMOS or PMOS FET? Explain how you can tell this. f. What is the majority carrier (i. e. charge type) used by the transistor when it is on? g. What is the purpose of the n+ region inside the n-well region? h. Calculate the intrinsic gate capacitance if W = 0.5 μm, L = 0.25 μm, and the oxide thickness is 54 Å. Fig. 2 CMOS device cross-section #2
In the MOSFET circuit below, let A and B be the inputs (0 V or 5 V, corresponding to 0 or 1) and let Z be the output. Construct the Truth Table for Z. What logic function does this circuit implement?
a. For the following three circuits, the capacitor is initially discharged (VOUT = 0 V), VDD = 1.8 V, both NMOS and PMOS devices have a |VT| = 0.5 V, and C = 2 pF. Find the steady-state VOut value and the energy stored in the capacitor at this voltage. b. For the following three circuits, the capacitor is initially charged (VOuT = 1.8 V), VDD = 1.8 V, both NMOS and PMOS devices have a |VT| = 0.5 V, and C = 2 pF. Find the steady-state Vout value and the energy stored in the capacitor at this voltage.
A circuit using a p-channel MOSFET is shown below. The MOSFET parameters are shown next to the circuit diagram. MOSFET Parameters Vt = 1 V Kp = μpCoxW/L = 2.22×10−3 A/V2 VA = 250 V a. What is the dc operating point VSDQ and IDQ? b. What are the values of gm and r0 of the MOSFET?
[2.1] Suppose that VDD = 5 V and VTn = 0.7 V. Find the output voltage Vout of the nFET in Figure P2.1 for the following input voltage values: (a) Vin = 2 V; (b) Vin = 4.5 V; (c) Vin = 3.5 V; (d) Vin = 0.7 V.
[2.2] Consider the two-FET chain in Figure P2.2. The power supply is set to a value of VDD = 3.3 V and the nFET threshold voltage is VTm = 0.55 V. Find the output voltage Vout at the right side of the chain for the following values of Vin : (a) Vin = 2.9 V; (b) Vin = 3.0 V; (c) Vin = 1.4 V; (d) Vin = 3.1 V.
Q1. For the figure shown, Let VDD = 1.2 V, Kn = 200 uS and Vth = 0.4 V where ID = 12 Kn(VGS − Vth)2 find the maximum value of R that will ensure operation in saturation region and find the maximum gain achievable at that R value in the following conditions: a) v1 = 0.5 V b) v1 = 1 V Plot GMAX(RMAX) versus v1 and RMAX versus v1 in the same plot (use two y-axes right and left) for v1 = (0.5: 0.01: 1.2)V You can use any plotting software (MATLAB, Excel . . . etc)
In Figure 5, the NMOS inputs are VA = VB = 5 V, the threshold voltage is Vtn = 2.8 V, and the initial output voltage is VO = 0 V. Provide an estimate for the output voltage. In Figure 5, the PMOS inputs are VA = VB = 0 V, the threshold voltage is Vtp = 3.2 V, and the initial output voltage is VO = 5 V. Provide an estimate for the output voltage.
The Transistors in the circuit given below are characterized by: Vtn = 0.6 V, kn′ = 100 μA/V2, VA−20 V, and (W/L) for Q1 = 40. If VDD = 3.3 V, calculate the following: (a) The value of the resistor R that sets IREF to 200 μA (b) (W/L) for Q2 to set the output current Io to 800 μA
Find the logical efforts of the following inputs in the CMOS circuit below. (a) Logical Effort of Input A: Rising: 3 Falling: 13/6 (b) Logical Effort of Input B: Rising: 7/3 Falling: 13/3
Using Boolean algebra or other simplification techniques, the Boolean expression F(a, b, c) = ab′c′ + ab′c + abc + a′b′c′ + a′bc′ simplifies as follows: F(a, b, c) = a′c′ + ac + b′c′ (You need not demonstrate this simplification as part of this assignment. Just implement the simplified expression. ) In your renamed transistor models Verilog file, complete the module for a circuit using only CMOS transistors that models the simplified version of the Boolean expression shown above. Use the module named sop_t. Tip: There is more than one way to define this function as an interconnection of other gates. You should keep transistor efficiency in mind when designing and modeling your solution. Recall: CMOS means complementary pairs of n-type (NMOS) and p-type (PMOS) MOSFETs. All circuits in this assignment and course must be implemented using CMOS processes.
An NMOS is to be used as a digital switch in an IC circuit, and currently has the following properties: μn = 450×10−4 m2 V.s, Cox = 8.6×10−3 F m2, W = 0.72 μm, L = 0.18 μm, tox = 4 nm, Vtn = 0.8 V. a) State the mode of operation and the required voltage for rDS = 2 kΩ. b) Adjust the width of the channel to obtain rDS = 1 kΩ. c) Select a different tox to obtain rDS = 1 kΩ.
Draw the Bode magnitude and phase plot of the following simplified 2-stage CMOS amplifier. With gm1 = Gm = 5 mS, ro2//ro4 = R01 = 100 Kohm, Cg6 = C1 = 50 pF, gm6 = 1.3 mS, ro6//ro7 = R02 = 45 kohm, CL = C2 = 30 pF. Find the angular frequency at 0 dB gain. Find the phase angle at the 0 dB gain angular frequency. Is this amplifier stable? Make sure to label the values of the slopes as well as the dB levels and phases of all horizontal slopes.
Use pole splitting and add a compensation capacitor Cc to the previous amplifier so that it provides a phase margin of 30∘. a) Draw the simplified equivalent circuit including Cc. b) Find ωP2. c) Choose phase margin ( 30∘ in this case). d) Find ω at which angle = (−180∘+ phase margin ). e) Make gain = 0 dB in magnitude plot at ω found in d) f) Find ωP1. g) Calculate Cc. h) Draw the new Bode magnitude and phase plots indicating the phase margin.
For a class-A power amplifier in Figure 3 , the Q-point is located at IDQ = 250 mA and VDSQ = 8 V Due to the input signal, the output drain current goes in between 450 mA & 40 mA. The VD swings between 15 V and 1 V. Determine (a) the output power delivered, (3 marks) (b) the input power, (3 marks) (c) conversion efficiency, ( 2 marks) (d) power dissipated by the MOSFET. (2 marks) Figure 3.
Fig. 21 shows a telescopic-cascode op amp. Assume that |Vov | of all transistor is 0.3 V, threshold voltages Vtm = 0.7 V, |Vtp| = 0.8 V and VDD = 3.3 V. (a) Find the input common-mode ranges. (b) Assume that all inputs are biased at 1.65 V, please find the output swings. Fig. 21
For the following circuit: a. Is this a Moore or Mealy model (5 points)? b. Write the flip flop input and next state equations (20 points), c. Write the output equation (5 points) d. Complete a state table for the circuit ( 20 points) e. Complete the timing trace as far as possible (20 points) (Assume both flip-flops are connected to a shared clock.)
The circuit in the figure is a two-input CMOS logic gate. a) Under the assumption that EN = VDD, write the truth table for the circuit (where IN1 and IN2 are the input signals and OUT is the output signal). (2) b) Again with EN = VDD, which is the logic function implemented by the circuit? (2) c) What is the static power dissipation of the circuit? (2) d) What is the state of the circuit at the output if EN = 0? (2)
For the circuit in Figure Q1, VDD = 4 V, Iref = 0.4 mA, (W/L)1 = 1, (W/L)2 = 2, (W/L)3 = 2, (W/L)4 = 8, (W/L)5 = 24, and (W/L)6 = 6, VtP = −1 V, and kp′ = 5 mA/V2. (a) Find Iout. (b) What are the DC voltages at nodes X and Y. (c) If |VA| = 20 V for PMOS transistors, find Rout. Figure Q1
For the amplifier circuit in Figure Q3, Vpo = 5 V, R1 = R2 = 500 kΩ, and CC is a large capacitor (open for DC analyms, short for small-signal analysis). The transistors are characterized by the following parameters: Vtn = |Vtp| = 1 V, kn = kp, = 2 mA/V2, and VAn = |VAp| = 10 V. Please answer the following questions. (a) Find the current flowing through the transistors. Ignore channel length modulation for this part. (b) What is the DC gain of the amplifier? (c) What is the input impedance of the amplifier? (d) What is the output impedance of the amplifier? Figure Q3
Q1. A) Sketch a static CMOS gate computing the following equation. You may assume you have both true and complementary versions of the inputs available. Y = (B⋅(A+C)+D)⋅(A+D)¯ B) Design the size of transistors in a way that tpdr = tpdf . Explain the different steps that you took to reach the final answer. Wmin = 200 nm L = 60 nm μn = 2μp VDD = 1.0 V C) First, convert the circuit to its RC model. Then, estimate tpd of the designed circuit using the Elmore delay model. Suppose that a unit transistor has R = 10 k and C = 0.1 fF and your circuit is deriving a 20 FF capacitance (a 20 fF capacitor is connected to the output).
The switches in the figure A can be implemented using MOSFETs, as shown in the figure B. What are the W/L ratios of the transistors if the on-resistance of the transistor is to be less than 1 percent of the resistor 2R = 10 kΩ? Use VREF = 3.0 V. Assume that the voltage applied to the gate of the MOSFET is 5 V when b1 = 1 and 0 V when b1 = 0. For the MOSFET, VTN = 1 V, Kn = 50 μA/V2, 2φF = 0.6 V, and γ = 0.5 V. (Round the final answer to the nearest whole number.) The ratio is W/L = 221/1.
For each of the following circuits, calculate the unknown steady-state voltage assuming that there is a path of "on" transistors through the circuit initially. Assume Vtn is 0.4 V and Vtp is −0.5 V : a) b) c)
Voltage Transfer Function These are the parameters of NMOS and PMOS transistor, μnCox = 2.5μpCox = 20 μA V2, |Vtn| = |Vtp| = 1 V, (W L)n = (W L)p = 30 μm 10 μm for the circuit given below. Do the following a) Find the region NMOS and PMOS operating b) Find the voltage Vout. c) Find the current Id. d) By keeping the (W L)n same find the new (W L)p which will ensure Vout = 1.5 V Ignore the body effect. Figure 3 CMOS based circuit
PMOS as a nonlinear resistor The PMOS transistor in the circuit of Fig P4.36 (as shown below) has Vt = −0.7 V, kp, = 0.06 mA/V2, L = 0.8 μm and λ = 0. Find the value required for W and R in order to establish a drain current of 115 μA and a voltage VD of 3.5 V.
For the following CMOS circuit, the parameters for the PMOS(Qp) are: KP = μpCox(W/L) = 4 mA/V2 and VtP = −2 V and the parameters for the NMOS (QN) are: KN = μnCox(W/L) = 4 mA/V2 and VtN = 2 V If the input voltage is high (VI = VDD = 5 V), what are the values of the output voltage V0 and load current IL ? Hint: MOSFET working in a certain region of operation can be replaced by a resistor a. VO = 0, IL = 0 b. VO = 0.192 V, IL = 0.385 mA c. VO = 0.385 V, IL = 0.192 mA d. VO = 0.385 V, IL = 0.385 mA e. VO = 0.185 V, IL = 0.185 mA f. None of these answers
Consider the following MOSFET Amplifier where M3 and M4 form a current mirror. The parameters of the transistors are kn′ = 0.2 mA/V2, VTH = 0.4 V, and λ = 0 (a) Find the value of Rm such that ID1 = 0.1 mA. Assume (W/L)1 = (W/L)2 = 5. Rm = kΩ (b) Find the value of RD that places the transistor M1 100 mV away from the triode region. RD = kΩ (c) What is the required W/L of M3 if the circuit must provide a voltage gain of 50 with the value of RD obtained in (b) (W/L)3 = Write your answer rounding to 3 significant digits. Examples: 0.357, −2.48, 13.0, −924, 3450
CMOS circuit: If there is a leakage with the PMOS transistor, the leakage can be modeled as a resistor R1 = 50 kΩ as shown in the figure below. tPHL will compared to R1 = ∞ (2 pt) (a) increase; (b) decrease; (c) Stay the same tPLH will compared to R1 = ∞ ( 2 pt) (a) increase; (b) decrease; (c) Stay the same
An NMOS transistor gate is controlled by the signal X as in Figure 1. Initially X = 0, and the capacitor was discharged to 0 V. When X is switched to logic 1 (VDD), C charges. (a) Derive an expression for the energy dissipated in the NMOS transistor when X is switched to logicShow all your steps clearly. (b) Calculate the above energy in joules, when VDD = 5 V, VmI = 1 V, and C = 100 fF(1 fF = 10−15 F). Figure 1. An NMOS circuit
Exercise 5 Consider the circuit below consisting of diode-connected NMOS transistors. Assume K′ = 100 μA/V2 and VT = 0.5 V. Note our class notation where we defined K = K′(W/L) for an NMOS transistor. (a) Prove that a diode connected NMOS always operates in the saturation region if it is ON. (b) Given the current and voltage values below, find the (W/L) values for each transistor. (c) Why is connecting the drain of an NMOS to its gate terminal called "diode-connected"?
Problem 3: Consider the following circuit which shows a pass-gate logic network. (a) Determine the truth table for the circuit. What logic function does it implement? (b) Assuming 0 and 2.5 V inputs, size the PMOS transistor to achieve an output node (OUT) voltage, VOL = 0.2 V. (VTHP = VTHN = 0.5 V ) Assume VOL is small enough so that higher order terms of VOL can be neglected in the IDs expression of NMOS transistors. Also, assume μn/μp = 2. (c) What will be problem(s) if the PMOS is removed?
QUESTION 2 (Current Mirror) Determine an expression for RP so that I1 = IREF/2 for the circuit shown in Figure 2. Find this expression in terms of IREF, and other transistor parameters (μCox, (W/L) ) Assume that both transistors are identical, i. e. , [μCox(W L)]REF = [μCox(W L)]1, VthREF = Vth1
All the MOSFETs for the circuits in Question 6 are from a 180 nm CMOS process for which the following parameters are given: μnCox = 100 μA/V2, μpCox = 40 μA/V2, Vtn = 1 V, Vtp = −1 V, λ = 0.01 V−1. Fig. for Question 6(a) Fig. for Question 6(c) (a) For the circuit shown in Fig. for Question 6(a), W = 10 μm, L = 1 μm. Find the resistance value R such that the voltage VD = 3 V. (b) Since resistance takes a lot of area in IC, you are asked to implement the circuit using an additional MOS transistor Q2. Show your circuit and find the W/L ratio of Q2.
The PMOS transistor network of a CMOS logic function is shown in Figure 1. All transistors used are of size 30/2. Find the size of an equivalent PMOS transistor for the input values shown. PMOS Network
Consider the circuit shown. Regardless of the values of any components or transistor parameters, the following statements are true: (select all that apply; wrong answers are penalized) VGS1 = VGS2 VGS2 = VGS3 ID1 = ID2 ID2 = ID3 None of the above
Consider the circuit shown. Given ID1 and VGS1, which of the following quantities are affected by the size (W/L) of M2? (Select all that apply; wrong answers are penalized) VGS2 VGS3 ID2 ID3 None of the above
Consider the circuit shown. Given ID1. ID2, and VGS2, and assuming M2 is in saturation, which of the following quantities are affected by the size (W/L) of M3? (Select all that apply; wrong answers are penalized) VGS1 VGS3 Iref ID3 None of the above
Consider the circuit shown. Assume that all the MOSFETs are operating in saturation. Iref = 28 μA. M2 has twice the width of M1 but otherwise the two MOSFETs are identical. Determine ID. Enter your answer in μA rounded to one decimal place. Your Answer: Answer
Consider the circuit shown. Assume that all the MOSFETs are operating in saturation. Iref = 26 μA and VGS2 = 0.50 V. M2 has 4x the width of M3 but otherwise the two MOSFETs are identical with VT = 0.4 V. Determine VGS3. Enter your answer in V rounded to two decimal places. Your Answer: Answer
Consider the circuit shown. Assume that all the MOSFETs are identical with VT = 0.4 V. VDD = VSS = 1.8 V. VGS2 = 0.54 V. Determine the smallest value of vI that allows M2 to remain in saturation. Enter your answer in V rounded to two decimal places. Your Answer: Answer
For the common drain amplifier the NMOS transistor has VT = 0.45 V, μnCox = 270 μA/V2, W/L = 10, VDD = 1.8 V, and λ = 0.08 V. Neglecting the body effect. The circuit is biased with VG = 1.63 V and IB = 200 μA. (a) Find the DC value at the source terminal. (b) Including the output resistance of current source IB, Find the expression of voltage gain and output resistance. (c) If current source IB has an output resistance of 100 kΩ(RL = ∞), calculate the voltage gain and the output resistance. (d) If current source IB has an output resistance of 100 kΩ and the load of 10 kΩ is also connected, calculate the voltage gain.
Fig. 3 depicts the measured Id−Vd curve for an n-channel silicon MOSFET with Tax = 5 nm, L = 0.1 μm, W = 14 μm, low field mobility (μo) = 490 cm2/V.s and electron velocity saturation (Vsat ) = 5×106 cm/s Extract the output resistance at the operating point "A". [1 marks] Find the transistor threshold voltage at Vd = 2 V. [1 marks] Extract the small signal equivalent circuit parameters at the operating point "A" for low frequency applications. [1 marks] Find the threshold voltage at Vd = 200 mV if the DIBL coefficient is 110 mV/V. [1 marks] Estimate the effective mobility at Vg = 1.5 V and mobility degradation factor. Assume Rds = 55 Ω. Fig. (3)
A transistor schematic diagram of a digital circuit is shown below (Fig. 3.1). The sizes of the MOS transistors are given as (W/L)1 = (W/L)2 = 16 and (W/L)3 = 4 with VTn = 0.5 V and μnCox = 10−4 A/V2. VDD = 1.8 V. Fig. 3.1 (a). What logic gate is the above digital circuit? Draw the logic gate symbol of the above digital circuit. (b). Determine the approximate output voltage Vout for the following given input voltages Vinl and Vin 2 in the static case. (c). When both the inputs Vin I and Vin 2 are connected to VDD, determine the output voltage Vout. . (d). Now, only the p-type MOSFETs with |VTp| = 0.5 V and μpCox = 5×10−5 A/V2 are available. Draw a schematic circuit diagram of such a logic gate implemented using only p-type MOSFETs. You must use standard circuit symbols and show the signal interconnections clearly with proper labels.
Example 7: The transistor parameters for the common-source circuit in Figure below are VTH = −0.4 V, (W/L)P = 50, λN = 0.02 V−1, λP = 0.04 V−1, k′n = 100 μA/V2, and k′p = 40 μA/V2 and ID = 0.5 mA. a) Determine (W/L)N such that the small-signal voltage gain is Av = Vout/Vin = −40. b) What is the required value of VB ? c) What is the value of VGS?
In this question we will consider feedback. Let R1 = 9 kΩ and R2 = 1 kΩ. CB is a big capacitor (open at DC and short at AC). (70 pt) a) What is the feedback type? What is the feedback factor f ? (10 pt) b) Ignoring feedback loading (ignore R1 and R2), what is the open loop gain a, loop gain T and closed loop gain ACL? (30 pt) c) Ignoring feedback loading What is the output resistance of the OPAMP and feedback? (10 pt) d) Repeat steps b) and c) without ignoring feedback loading (i.e. add R1+R2 load at the output) (20 pt)
Below is the CMOS diagram of a logic gate that has two inputs A and B and a single output Y. VDD is a logic 1, and ground, represented by a triangle, is a logic 0. a) Fill in the table below. State if P or N-type transistors are ON or OFF, and provide the logic output of Y.
The current-mirror-loaded differential amplifier in Fig. 5 has a feedback network consisting of the voltage divider with R1 = R2 = 25 kΩ. All the devices are sized to operate in saturation and |VOV| = 0.2 V (overdrive voltage). For all devices, Early voltage |VA| = 10 V. The input signal source has a zero dc component. Assume VDD = 5 V and VSS = −5 V. (a) (10 points) Find the gm and ro values for the transistors Q2 and Q4. (b) (10 points) Find the closed-loop voltage gain vo/vs.
The differential amplifier of Fig. 5 is biased with I = 100 μA. All transistors have L = 2 μm, and Q1 and Q2 have W/L = 50. All transistors are operated in saturation region. The circuit is fabricated in a process for which μnCox = 200 μA/V2 and |VA′| = 5 V/μm. Find gm1, 2, ro2, ro4, and Ad = vo/vid. Fig. 5
Consider the amplifier of Fig. 10.74, where (W/L)1−4 = 50/0.5 and ISS = I1 = 0.5 mA. (a) Estimate the poles at nodes X and Y by multiplying the small-signal resistance and capacitance to ground. Assume that CX = CY = 0.5 pF. What is the phase margin for unity-gain feedback? (b) If CX = 0.5 pF, what is the maximum tolerable value of CY that yields a phase margin of 60∘ for unity-gain feedback? Figure 10.74
Exercise 8.4 Consider the MOSFET amplifier shown in Figure 8.3. Assume that the amplifier is operated under the saturation discipline. In its saturation region, the MOSFET is characterized by the equation iDS = K 2 (vGS − VT)2 where iDS is the drain-to-source current when a voltage vGS is applied across its gate-to-source terminals. Figure 8.3: a) Write an expression relating vO to vI. What is its operating point output voltage VO, given an input operating point voltage of VI ? What is the corresponding operating point current IDS ? b) Assuming an operating point input voltage of VI, derive the expression relating the small signal output voltage vo to the small signal input vi from the relationship between vO and vI. What is the small signal gain of the amplifier at the input operating point of VI ? c) Draw the small signal equivalent circuit for the amplifier based on the SCS model of the MOSFET assuming the operating point input voltage is VI. d) Derive an expression for the small signal gain of the amplifier from the small signal equivalent circuit. Verify that the gain computed from the small signal equivalent circuit is identical to the gain computed in part (b). e) By what factor must RL change to double the small signal gain of the amplifier? What is the corresponding change in the output bias voltage? f) By what factor must VI change to double the small signal gain of the amplifier? What is the corresponding change in the output bias voltage?
a) (4 marks) Implement the following Boolean expression using CMOS complex logic gates: Y = (A¯ + B¯)⋅C¯ + (D¯⋅E¯) b) (1 mark) Label the worst-case current path for the PUN. The designed CMOS complex logic gate drives an inverter load as shown in figure below. Given: Cwire = 100 fF, cox = 100 fF/m2, Ln = Lp = Lmin = 0.5 μm, VTn = |VT|p = 1 V Assume that Wp (all PMOS identical) = 2Wn (all NMOS identical) (7 marks) c) Calculate CL and estimate the rise time delay (tr) when the system implements Z = 0 with A = B = C = 1, D = E = 0.
In the complex gate below, nMOS transistor E is sized as 2 W times wider than a unit inverter. a. Give each transistor a width that makes it "compatible" with transistor E's width of 2 W. b. What is the nominal ON resistance in relation to that for a unit inverter (R)? c. Draw a stick diagram for this cell. Note the left-most poly is input B. d. What is Cout (total diffusion capacitance on Y)? c. Compute Cin for inputs A, B, C, D, and E. f. What is the logical effort for his gate as seen by input A? N+ P+ Poly Metal1
A 3-bit parity checker counts the number of 1's in a sequence of 3 bits and outputs 1 if odd, 0 if even. (Example: If the input is 101 , output is 0 , but if the input is 001, output is 1). Knowing that: VTn = 0.53 VVTp = −0.51 VμnCox = 98.2 A/V2 μpCox = 46 A/V2 VDD = 1.2 VEc,nLn = 0.45 Ec,pLp = 1.2 and the output load capacitance is 30 fF: a) Draw the CMOS transistor-level of the complex logic gate. b) Compute the (W/L)n of the nMOS transistors such that the equivalent inverter of the complex logic gate has τPIn = 20 ps using the average method. c) Draw the pseudo-nMOS transistor-level of the complex logic gate. d) Compute the worst-case VOL of the equivalent inverter if (W/L)p = 4 and (W/L)n = 1.
Consider the CD-CG amplifier of Fig. 10.41(c) for the case gm = 5 mA/V, Cgs = 2 pF, Cgd = 0.1 pF, CL (at the output node) = 1 pF, and Rsig = RL = 20 kΩ. Neglecting ro, find AM and fH. (Hint: Evaluate fH directly from the transfer function.) Fig. 3
You are asked to design an NMOS inverter with a resistive load, as shown in Figure 2.e, with the input voltage of either 0 V (logic level 0 ) or 3.3 V (logic level 1). The transistor is an n-channel enhancement type MOSFET with a threshold voltage of VT = 1.5 V, an aspect ratio (W/L) of 20, and a gate capacitor per unit area of 400 nF/cm2. The electron mobility is 500 cm2/Vs. When the input is at logic level 1 (vi = 3.3 V), the transistor is in the linear region. Find the values of VDD and RD to have the output voltage of 0.3 V at logic level 0 and 3.3 V at logic level 1. Figure 2.e.
For a MOSFET biased in the triode region, we can define an equivalent drain-source resistance as rDS,tri = (∂ID ∂VDS)−1 Derive an expression for this quantity and compare it with the equivalent resistance in the deep-triode region Ron we derived in class. Also plot rDS,tri as a function of VDS.
Below figure depicts a cascode current source whose value is defined by the mirror arrangement, M1−M2. Assume W/L = 4,3 μm/0,18 μm for M1−M3. Select the minimum tolerable value of Vb so that Iout is equal to 0.5 mA. Circuit parameters / Devre Parametreleri μnCox = 200 μA/V2, VTH = 0.4 V, λ = 0. a. 1.56 V b. 0.96 V c. 0,56 V d. 2,06 V e. 1,31 V f. 0,76 V g. 1,16 V
3.13 Shown in Fig. 3.66 is the circuit schematic of an amplifier stage built with a self-biased inverter. Both MOSFETs operate with source-bulk shorts. Draw the high-frequency small-signal equivalent circuit of this stage without showing ineffective components. Figure 3.66
5.29 Fig. P5.29 shows two NMOS transistors operating in saturation at equal VGS and VDS. (a) If the two devices are matched except for a maximum possible mismatch in their W/L ratios of 2%, what is the maximum resulting mismatch in the drain currents? (b) If the two devices are matched except for a maximum possible mismatch in their Vt values of 10 mV, what is the maximum resulting mismatch in the drain currents? Assume that the nominal value of Vt is 1 V. Figure P5.29
Analyse the performances of the BJT and the MOSFET in the circuit of Figure 4 by determining a value for RE to set ID to 4 mA IDSS = 18 mA, VP = −3 V, VDD = 25 V, VEE = −12 V, RG = 330 kΩ, RD = 2.2 kΩ. Figure 4: MOSFET and BJT circuit
The circuit in the figure is a two-input CMOS logic gate. a) Find the voltage at the output for (IN1 = VDD, IN2 = VDD) and for (IN1 = 0, IN2 = 0). (2) b) Write the truth table for the circuit. Which is the logic function implemented by the circuit? (2) c) How much power does the circuit consume in the two conditions given in question a)? Justify your answer. (2)
Problem 3− A bridge diode rectifier circuit is shown with a low-pass filter. Assume each diode drops 0.7 V when conducting, the AC source is VS = 10 V rms and 60 Hz. Let R = 1 KOhm and the capacitor C = 1 μF. A) Find the pick voltage Vp at the output port Vo. B) Find the voltage drop, Vγ, at the output Vo. C) Find the amount of PIV effecting the diodes.
If a CMOS inverter has W/Ln = 16.3, what value must the PMOS W/L have to make this inverter symmetric? Use: VDD = 2.5 V, VTN = 0.4 V, VTP = −0.6 V, k′n = 150 μA/V∧2, k′p = 60 μA/V^2 Answer:
P11.35. Both transistors shown in Figure P11.35 have KP = 100 μA/V2 and Vto = 0.5 V. Determine the value of R needed so that iD1 = 0.2 mA. For what range of Vx is the second transistor operating in the saturation region? What is the resulting value of iD2? Provided that Vx is large enough so that the second transistor operates in saturation, to what ideal circuit element is the transistor equivalent? Figure P11.35
The NMOS transistor below has Vt = 0.6 V, and VA = 5 V which means channel effect is considered. The dc voltage at the source is measured as −0.8 V. Assume all three capacitors to be ideal (infinite large). Here RD = 9 kohms and RG = 20 Mohms (a) What is the dc voltage at the drain terminal? (b) What is the overdrive voltage at which the transistor is operating? (c) What is the region in which the MOSFET is operating? (d) Find the values of gm and ro. (e) Now assume Y is connected to ground and a small signal vx is at X, find the input resistance Rin and overall voltage gain vx/vz. Please round overall voltage gain Gv to the nearest two decimal places.
The MOSFET as shown has Vt = 0.5 V. No channel effect is considered here. The dc voltages at the source and drain terminals are measured and found to be −0.9 V and +2 V, respectively. Assume all three capacitors are ideal. (Infinitely large) (a) Calculate overall gain Gv when switch goes to 1. Please round to the nearest two decimal places. (b) If the switch goes to 2 the amplitude of the output v0 is halved (half the original value), in this case what is the value of RS ? Please round the nearest whole resistor value.
a) Consider the NMOS circuit given in Fig. 3. Assume VDD = 15 V. Determine the value of RF to set the current IR = 1 mA, using the transistor parameters VTN = 1.2 V, KN = 0.43 mA/V2. Fig. 3. NMOS Circuit b) Add MO and RO to the circuit as given in Fig. 3 as shown in Fig. 4; to form a simple current mirror to be used as a current source. Assume MR and M0 are matched with the same parameters. With VDD = 15 V, and the value of RF as obtained in part (a), and RD = 5 kΩ determine Io and VDSO. Fig. 4. Simple Current Mirror
Problem 1 (5 points): Given Table 1, the goal is to derive the important device parameters from these data points. As the measured transistor is processed in a deep-submicron technology, the 'unified model' holds. From the material constants, we also could determine that the saturation voltage VDSAT equals −1 V. You may also assume that −2ϕF = −0.6 V. a. Is the measured transistor a PMOS or an NMOS device? Explain your answer. b. Determine the value of VT0. c. Determine γ. d. Determine λ. e. Given the obtained answers, determine for each of the measurements the operation region of the transistor (choose from cutoff, resistive, saturated, and velocity saturated). Annotate your finding in the right-most column of the above. Table 1 Measurements taken from the MOS device, at different terminal voltages.
M1 and M2 are saturation. Neglect the body effect. Derive an expression for the low frequency output resistance, Rout, in terms of the MOS small signal parameters.
Consider the CMOS complex gate in the figure, whose pMOS network is shown as a box. a) Express the realized logic function and then draw the complete circuit, by drawing the pMOS transistors as well (Redraw nMOS transistors as they are, because you will need them in (b) and (c)) b) Assign each transistor its relative size, such that charging and discharging resistors (corresponding to propagation delays) are same as those of a unit inverter (Assume μn ≈ 2μp ). c) Determine and indicate parasitic capacitances at each relevant node, in terms of unit capacitance C (Consider drain/source capacitance halving only for merged+uncontacted diffusions). Then, express the rising and falling propagation delays ( tpLH and tpHL ) in terms of R and C (Use 0.69 factor as well and include Elmore delays). d) Assume that, as a designer, you feel that the pull-down delay can be improved if the positions of A−D and C-B nMOSTs are replaced (C-B close to the output; A-D close to the ground). Redraw the circuit for this new placing (only nMOSTs are replaced), indicate the relevant parasitic node capacitances and re-calculate tpHL to see if there is an improvement. It will be better if you add your comments as well.
A cascode current mirror circuit is shown in Fig. 3. The device parameters are given as μnCOX = 300 μAV−2, VDD = 1.8 V, IREF = I0 = 12 μA, λN = 0.08 V−1, Vtn = 0.5 V, overdrive voltage VOV = 0.2 V, γ = 0, and neglect velocity saturation effect. Determine the minimum output voltage. [2 pts] Answer: V Mark each node voltages (in V ) of the current mirror circuit. [3 pts]Determine W/L ratio of M3 transistor in order to obtain the minimum output voltage. [3 pts] Answer: W/L = Determine R1 in the current mirror circuit. [3 pts] Answer: ΩDetermine Rout of the current mirror circuit. [3 pts] Answer: Ω Figure 3: Current mirror circuit.
The shown S-R Flip Flop uses matched inverters and is fabricated in a 0.18 μm technology with μnCox = 400 μA/V2, (W/L)n = 0.45/0.18, and PMOST with μpCox = 160 μA/V2, (W/L)p = 1.125/0.18, VDD = 1.8 V, Vtn = |Vtp| = 0.4 V. The drain node capacitance CQ is equal to 100 fF and CR,S = 5 pF. The circuit is at RESET state. One of the shown sub-circuit needs to be used to change the state to SET. Select such a circuit and: Justify rejection of others Determine the clock time needed for the SET state to be ensured Determine the maximum clock frequency
Consider this PMOS circuit: K = 0.2 mA/V2 Vt = -2.0 V For this problem, we know that the drain voltage VD = 4.0 V (with respect to ground), but we do not know the value of the voltage source VGG. Let's attempt to find this value VGG!
Consider the above MOSFET amplifier circuit and assume that the capacitors are infinitely large. MOSFET parameters are given to be: Vt = 0.9 V, and kn = 76 μA/V2. Component values are given as Rsig = 1.2 KΩ, R2 = 6 KΩ, RD = 3.4 KΩ, RS = 600 Ω and RL = 5.1 KΩ. Design the value for resistor R1 for setting an operating voltage of VDS = 12 V (express the result in KΩ units).
Question 3. The MOS differential amplifier shown in the figure utilizes a pair of matched PMOS transistors for which Vtp = −0.4 V, kp′ = 100 μA/V2, and W/L = 50. Channel length modulation can be neglected. a. For an input common mode voltage VCM within the input common mode range of the amplifier, what are the dc voltages at the drains? b. Find the input common mode range assuming that for proper operation the bias current source requires a minimum voltage across it of 0.2 V. c. What is the input differential voltage (vG1 − vG2) that steers the bias current entirely into Q1?
Problem 2: Consider the following NMOS inverter. Assume that the input IN has a 0 V to 2.5 V swing. Assume VT0 = (0.43 + X/100)V, where X is the last digit of your ID. Ignore channel length modulation. Ignore body effects. a) Find the voltage on node x. b) What is the range for VOUT as IN varies from 0 to 2.5. What is the mode of operation of M2 over that range. Use long channel regions to get a good guess?
For this quiz, Vdd is 3.3 V. The operating point of this circuit has been designed such that the gate overdrive voltage (VGS−VT) is 0.25 V for all transistors. The bias current is 100 μA. You can assume all gm≫ all gds. Remember, large caps appear as small signal shorts. Show your work on the attached sheet and be careful with units [Give your answer in kΩ to 4 decimal places, no units, no unit prefixes, no commas. Example: 2 kΩ → Answer Given: 2.0000 ] What is the small signal output resistance, Rout , at v0 looking back into the circuit?
The PMOS transistor in the circuit below has parameters Vtp = −1.2 V, kp′ = 35 μA/V2, and W/L = 15. Design the circuit so that iD = 0.25 mA and vD = −2 V.
For this quiz, Vdd is 3.3 V. The operating point of this circuit has been designed such that the gate overdrive voltage (VGS−VT) is 0.25 V for all transistors. The bias current is 100 μA. You can assume all gm≫ all gds. Remember, large caps appear as small signal shorts. Show your work on the attached sheet and be careful with units If you half the bias current, what happens to the small signal gain?
Consider the circuit shown in the figure. The PMOS has Vtp = −0.7 V and a very large |VA|. The value of RS is selected such that the transistor is biased at ID = 0.4 mA and |VOV| = 0.4 V. Assume vsig to have a zero dc component. Capacitors CS and CC have large values and can be considered as short circuit for all signal frequencies of interest. Determine the value of RD that results in Gv = vo/vsig = −12 V/V. Determine the value of RD that results in vo/vsig = −12 V/V. Express your answer in kΩ. Type in the numerical value of RD without the unit.
For this quiz, Vdd is 3.3 V. The operating point of this circuit has been designed such that the gate overdrive voltage (VGS−VT) is 0.25 V for all transistors. The bias current is 100 μA. You can assume all gm≫ all gds. Remember, large caps appear as small signal shorts. Show your work on the attached sheet and be careful with units [Give your answer in number form to 4 decimal places, no units, no unit prefixes, no commas. Be sure to include if it is positive or negative Example: - 2 V/V -- > Answer Given: −2.0000] What is the small signal voltage gain (vo/vin) of this circuit?
Consider the amplifier shown below. Draw the full small signal schematic, and use this to derive expressions for the total midband gain (vout/vsig), the input resistance (Rin), and the output resistance (Rout). Make your functions expressions of gm when necessary, you do not need to calculate bias points! Assume that the transistor operates in the saturation region. You may ignore the output resistance (ro) of the transistor.