10.2 A single-transistor DRAM cell is represented by the following circuit diagram (Fig. P10.2). The bit line can be precharged to VDD/2 by using a clocked precharge circuit. Also the WRITE circuit is assumed here to bring the potential of the bit line to VDD or 0 V during the WRITE operation with word line at VDD. Using the parameters given:VT0 = 1.0 Vγ = 0.3 V1/2 |2ϕF| = 0.6 V(a) Find the maximum voltage across the storage capacitor CS after WRITE-1 operation, i. e. , when the bit line is driven to VDD = 5 V. (b) Assuming zero leakage current in the circuit, find the voltage at the bit line during READ-1 operation after the bit line is first precharged to VDD/2.
A 1T DRAM cell is represented by the following circuit diagram. The bit line can be precharged to VDD/2 by using a clock precharge circuit. The write circuit is assumed here to bring the potential of the bitline to VDD or 0 during write operation with wordline at VDD. Using the parameter given: VTO = 0.4 V, γ = 0. a) Find the maximum voltage across the storage capacitor Cs after WRITE-1 operation, i. e., when the bit line is driven to VDD = 2.5 V. b) Assume that, the leakage current from the storage capacitor is estimated to be 500 pA and minimum voltage for logic ' 1 ' value is 1 V. Calculate hold time. c) Calculate required refresh rate.
Consider the single transistor (1T) DRAM cell circuit shown in figure above. It includes peripheral circuits which pre-charge the bitline BL during read operations and drive the bitline to 0 V or VDD during write operations. Cs = 50 fF and CBL = 450 fF. Assume the following parameters for the NMOS access transistor: W/L = 1 μnCox = 100 μA/V2 Vt = 1 V When writing a logical 1 into the DRAM cell, assume that the write circuit maintains the bitline at VDD = 5 V when the wordline WL is asserted and driven to VDD. What is the final voltage written onto the DRAM cell storage capacitor? 2. What are the advantages and disadvantages of 1-T DRAM cell over 6-T SRAM cell?
(A) (DRAM) A 1-T DRAM cell shown below consists of a single transistor connected in series with a capacitor. For a read, the bit line is precharged to VDD/2 by a clocked precharge circuit. Then, the access transistor is turned on by applying VDD to the word line. A write is performed by applying VDD or GND to the bit line and VDD to the word line. Assume that VT0 = 0.4 V, γ = 0.3 V1/2, |2 ΦF| = 0.6 V, and VDD = 2.5 V (i) Find the maximum voltage across the storage capacitor Cs after writing a 1 into the memory cell. Bit line is driven to VDD. (4 pts) (ii) Ignoring leakage currents, find the voltage on the bit line when this " 1 " is read from the memory cell. (4 pts)
A one-transistor DRAM cell consists of an NMOS transistor Q and a storage capacitor Cs. The gate of the transistor is connected to the word-line (Word i), and its drain (source) is connected to the bit-line (Bit j). Note that the bit-line has a capacitance CB much larger than the cell capacitance Cs. During a read cycle, the bit-line is always pre-charged to 0.5VDD volts. During a write cycle, the bit-line is raised to VDD volts in order to store a "1" in the cell, while the bit-line is reset to 0 volt, in order to store a "0" in the cell. a) Using charge conservation technique, derive an equation for the change in the voltage (ΔV) on the bit-line when the input voltage to the word-line is changed from 0 to VDD volts, connecting the storage capacitor CS to the bit-line. b) In a particular DRAM chip, CS = 30 fF, CB = 1 PF, VDD = 5 V, transistor's threshold voltage Vt = 1.5 Volts. Calculate the readout voltage (ΔV) for a stored " 1 " and a stored " 0 ".
The figure shows the schematic of a bit line in a single transistor DRAM memory. Assume that the bit line has 4096 (4K) such cells connected to it in each column, and that each cell is 1 μm×μm. Take the transistor diffusion junction capacitance contributing to the bit line capacitance for each cell to be 0.5 femtofarads (femto = 10−15 ) and the metal-over field oxide bit line capacitance to be 0.05 ferntofarads per sq μm. (a) Assuming a 0.25 μm wide bit line, (i. e. 0.25 μm technology), estimate the bit line capacitance for this memory. (b) If the bit line capacitance is C2, estimate C1 to achieve a 100 millivolt change on the bit line precharged to 1 volt when reading out a high stored in the cell (on C1) operating off a 2 volt supply. (i. e. C1 is initially charged to 2 volts before the transistor is turned on for readout. )
Problem 5. SRAM (22 pts) a. Considering the following 6T SRAM cell, please explain the sizing of N0, N1, and P1. What are the requirements on their relative strengths? (6 pts) b. For the 6T SRAM design, at what conditions, achieving the proper sizing will be difficult? (5 pts)
II. For the following DRAM cell, the bit line is precharged to VDD/2 by using a clocked pre-charge circuit. Also the "Write' circuit is assumed here to bring the potential of the bit line to VDD or 0 V during the 'write' operation with word line at VDD. VTO = 0.5 V, γ = 0.3 V1 /2 and |ϕs| = 0.6 V. Find the maximum voltage across the capacitor Cs after write " 1 " operation. Include body effect. VDD = 3 V. Assuming zero leakage current in the circuit, find the voltage at the bit line during read ' 1 ' operation after the bit line is first pre charged to VDD/2. If the transistor has a leakage current of 2 pA what is the maximum refresh time so that stored " 1 " across does not go down below 80% of initial maximum voltage across Cs. What is the refresh clock rate.
Consider the following 2 T DRAM design. All NMOS transistors are minimum sized ones with W/L ratio of 2:1. The drain diffusion capacitance and gate capacitance of the two transistors are Cd = 15 fF and Cg = 25 fF, respectively. Given k′ = μnCox = 100 μA/V2, Vt, n = 0.3 V, CRBL = CWBL = 400 fF, VDD = 1.5 V, γ = 0.15 V, 2φF = −0.6 V and when accessed WL = VDD and RL¯ = 0 V.
A 1-T DRAM cell as following consists of a single transistor connected in series with a capacitor. For a read, the bit line is precharged to VDD/2 by a clocked precharge circuit. Then, the access transistor is turned on by applying VDD to the word line. A write is performed by applying VD or GND to the bit line and VDD to the word line. Assume that VTo = 0.4 V, γ = 0.3 V1 /2, |2ϕF| = 0.6 V a) Find the maximum voltage across the storage capacitor Cs after writing a 1 into the memory cell (i. e. , bit line is driven to VDD = 2.5 V ). b) Ignoring leakage currents, find the voltage on the bit line when this " 1 " is read from the memory cell.
A DRAM cell uses a storage capacitor of 38 fF, VDD = 2.5 V and VT = 0.5 V for the NMOS access FET. If the bit line capacitance is 210 fF, the sense amp can detect voltages down to 19 mV as a valid one, and the memory is refreshed every 1 μsec, what is the maximum leakage current that can be tolerated in nanoamps? Answer: Check
There is a dynamic random access memory (DRAM). (1) What is the minimum capacitance of Cs to have higher than 3 V of Vf after READ operation? Assume Vs = 3.3 V, C Cbit is 1 fF. (2) DRAM requires refresh process because leakage makes the voltage at Cs decrease. What is the minimum refresh period to sustain the voltage Vs higher than 3.0 V ? Assume the leakage current is 1 nA, and Css is 20 fF. Ignore voltage decrease by charge sharing.
Consider DRAM based on 1-Transistor DRAM cell and operating at VDD = 2.5 V. Threshold voltage of NMOS is 0.5 V and precharge voltage of bitline is 1.25 V. Cell storage capacitance is 50 fF and the bit-line capacitance is 1 pF. How much voltage swing is created on the bitline when a cell storing ' 1 ' is accessed for the read operation? Select one: a. 59.5 mV b. 119 mV c. 35.7 mV d. 1.25 V e. 47.6 mV
Problem 2: DRAM operation In a 1T DRAM cell shown in Fig. 2, BL is precharged to VBL = VccA/2 = 1 V, and CS is initially discharged to GND. Assume CS = 20 fF, and CBL = 80 fF and Vth, M1 = 0.4 V. There is NO sense amplifier attached to the BL. Figure 2. A 1 T DRAM cell (a) When WL is applied with VccA = 2 V, the access transistor M1 will turn on. At this point, will the final BL voltage (VFinal ) increase or drop, compared with the precharge voltage? By how much (in mV) ?
Consider a DRAM cell using a power supply = 5.0 V to have the following specification: nFET Threshold voltage = 0.8 V; Storage capacitance = 62.85 fF; Bit-line capacitance = 457 fF; Leakage current when WL = 0:19 fA. a) Calculate time required to reduce number of stored electrons down to 5×105 from its maximum value after WL is set to low voltage 0 . b) Calculate the minimum refresh frequency if the bit line capacitor voltage must not be lower than 350 mV to detect a logic 1 state. c) At t = 0, the WL is raised to high voltage to write logic 1 on the storage capacitance, and then WL is set to low voltage. Subsequently, at t = 4.5 s, the WL is set to high voltage and a Read operation is initiated. Calculate the final voltage read on the bit-line.
[DRAM Analysis] Figure 4 shows a 1 μm×1 μm DRAM cell with NMOS width W = 0.5 μm and CS = 55 fF. Assume VDD = 1 V. Assume that for the NMOS transistor, CD = CG = 1 fF/μm, VTH = 0.2 V, Ileak, n = 1 nA for a W = 0.5 μm device. The cell is arranged in a 128×8 memory block and the wordline and bitline wires have a capacitance of CW = 0.2 fF/μm (i. e. 0.2 fF per unit length). Each bitline is connected to a sense amplifier with ΔVsense = 100 mV and input capacitance 5 fF, and you may ignore loading from any other peripheral circuitry. Use the ideal switch model for the transistor. Figure 4 (a) WRITE: Assume the cell initially stores a " 0 ". In order to write a "1", BL and WL are raised to VDD. What is the final value on node X ? (b) READ: After storing values in your memory, you pre-charge the bitline to VDD/2 and read. What is the final value on the bitline when you are reading a " 1 "?
Problem 1: Consider a DRAM cell storing logic ' 1 '. The storage capacitance of the DRAM cell is CS = 50 fF and the bitline capacitance is CBL = 450 fF. The supply voltage (VDD) is 1 V and the threshold voltage of the access device is VT = 0.5 V. The constant leakage current for the cell is 250 pA at room temperature (T = 300 K). (a) Find the minimum voltage boosting at the gate of access transistor so that storage capacitance can be charged to full 1 V supply level. Consider the role of body effect and use body effect coefficient (γ) as 0.3 V and φf = 0.35 V. (10 points) (b) Considering the constant leakage current, find the maximum refresh period that can be tolerated for the cell? If DRAM temperature rises to 350 K, what will be the new maximum refresh period that can be tolerated? (5+5 points)
The circuit shown below is a DRAM cell. The transistors have a threshold voltage of VT. The write world line (WWL) and the read word line (RWL) are low when there is no read or write operation. The bit line 2 (BL2) is pre-charged to a high value (VDD−VT) before a read operation. (a) Explain why BL2 needs to be pre-charged to a high value before a read operation. (2%) (b) What is the function of transistor M2 ? (2%) (c) Sketch the voltage waveforms at WWL, BL1 and X for a write operation. Assume a 1 is written into the memory cell. (4%) (d) Sketch the voltage waveforms at X, RWL and BL2 for reading the bit value stored in step (b). Is the read value an inverting or non-inverting value of the stored signal? (5%) (e) Give an advantage and a disadvantage of the DRAM compared to the SRAM. (2%)
A DRAM cell uses a storage capacitor of 20 fF, VDD = 3.0 V and VT = 0.5 V for the NMOS access FET. If the bit line capacitance is 273 fF, the leakage current is 3 nA, and the memory is refreshed every 3 μsec, then what is the minimum voltage in millivolts that the sense amp must be able to detect as a valid one? Answer: The correct answer is: 139.9
A 1 T-DRAM cell is given below where the cell node capacitance (Cs) is equal to 30 fF. The diffusion capacitance of the transistors in each cell is 0.5 fF (Cd). The metal resistance and the capacitance of the bit line are negligible. For the DRAM storing capacitance, only consider Cs. (50 pts) Vdd = 1 Vtn = 0.4 Vγ = 0 a) What is the change in bit line voltage during read-1 operation when there are N number of cells (columns) attached to the bit line? (15 pts) b) What is the maximum number of cells per bit line we can have if the bit line voltage swing during the read operation has to be at least 50 mV ? (3 pts) c) Why is the capacitor Cs connected to 0.5 Vdd and not 0 or Vdd ? ( 2 pts ) d) Assume that we have a 2 T-DRAM cell as below with 2 identical transistors. Separate signals are provided for read (RS¯) and write (WS) word lines. The bit line is pre-charged to Vdd/2 prior to read operation. Explain the operation of the memory (read0-1 and write0-1) with the values of each signal in the design. You need to explain the signals (parametric) properly to get the required points. (30 pts)