Consider a DRAM cell that uses an internal capacitor of 20 fF; it is charged to 3.3 V when storing a ' 1 '. In this problem, ignore body effect. (A real transistor like the access transistor here, or pass transistors in switch logic, can turn off before you want it to because of body effect; this one stays on until the 20 fF capacitor is fully charged. ) (6-points) (a) When writing a ' 1 ', how long does it take for the voltage on the capacitor to rise to 95% of its final value? Assume that when it is on, the access transistor in the cell has an average resistance of 6 kΩ; assume that the inverter driving the bit line has an average pull-up resistance of 1 kΩ. Ignore the resistance and capacitance of the bit line itself. (In a real memory, wire parasitics play a big role!)? (b) Suppose that when reading, the bit line is first charged to 3.3 V. The bit line is a large piece of metal, and has a total capacitance of 500 fF. How far does the bit line drop in voltage if a ' 0 ' is read? (Hint: In circuits, you learned that charge on capacitors in parallel redistributes until the voltage is equal; assume enough time is given for the bit line to drop as far as it ever will. )? (c) Suppose that the leakage current from the cell, due to the reverse-biased diode and subthreshold MOSFET currents, is no more than 2 pA. If a signal loss on the capacitor of 0.5 V can be tolerated, how often must the DRAM cell be refreshed to ensure that no data is lost?
A DRAM cell uses a storage capacitor of 38 fF, VDD = 2.5 V and VT = 0.5 V for the NMOS access FET. If the bit line capacitance is 454 fF, the sense amp can detect voltages down to 28 mV as a valid one, and the memory is refreshed every 9 μsec, what is the maximum leakage current that can be tolerated in nanoamps? The correct answer is 6.9
(a) Assume that the MOSFET in Figure 3.1 is operating in saturation and is characterised by a threshold voltage, VT = 1 V. Assume that the parameter, K = 1 mA/V2 where the drain-source current in the MOSFET in saturation is given by the usual expression: iDS = K2(vGS−VT)2 Calculate the output voltage, vo, for the circuit shown in Figure 3.1 when vIN = 2.5 V, Vs = 10 V, and R = 1 kΩ. The correct solution should satisfy both conditions necessary for the device to operate in saturation. Figure 2.1 [10 marks] (b) For the circuit in Figure 2.1, calculate the small signal voltage gain of the circuit, Av, at the operating point defined by the numerical values of part (a). Assume the input and output voltages include small signal components, vin and vout respectively. VIN and Vout correspond to the constant DC components of the input and output voltage from part (a). vIN = VIN +vin vOUT = VOUT +vout Av = vout vin [10 marks] (c) Determine the small signal output impedance at the terminals labelled a and b for the circuit shown in Figure 3.1 and at the operating point defined by the numerical values of part (a). [10 marks]