For the circuit in Fig. 3 assume VDD = 2.6 V, Ibias, and the bias voltage, Vbias, are; a) 0.9 mA, 1.25 V b) 9 μA, 1.1 V c) 9 μA, 1.0 V d) 90 μA, 1.0 V e) None of the above Fig. 3 CMOS Bias Circuit
Q2. The following circuits use MOS transistors with the following parameters; Vtnn = 0.4 V, VTp = −0.4 V, kn = 400 μA/V2 and kp = 100 μA/V2. Assume λ = γ = 0. (8 pts) For the circuit in Fig. 2 assume W/L = 5/1 and R = 2kΩ. The reference current, Iref , and drain-source voltage VDS, are; a) 2.5 mA, 0.5 V b) 0.65 mA, 1.5 c) 0.8 mA, 1.2 V d) 0.65 mA, 1.2 V e) None of the above Fig. 2 MOSFET Bias Circuit
(25 pt) Q3. The following is a CMOS amplifier. Assume VDD = 5 V, RF = 750 kΩ, RL = 1 MΩ, VTn = 0.5 V, VTP = -0.5 V, kn = 400 μA/V2, and kp = 100 μA/V2, λn = λp = 0.02, (W/L)1 = 40 /1, (W/L)2 = 100 /1. a) Find the Q-point (ID1, VDS1, and ID2, VDS2). For this part (a) assume λn = λp = 0. b) Calculate the voltage gain (Av = Vo/Vt). For this part (b) and parts (c) and (d) assume λn = λp = 0.02 c) Determine the input resistance (Ri). d) Calculate output resistance (R0).
A CMOS amplifier is shown in Figure 3. PMOS transistors M1 and M2 have μpCox = 60 μA/V2, Vtp = -0.4 V, |1/λp| = 100 V, W = 240 μm and L = 1.6 μm. The NMOS transistor M0 has parameters μnCox = 90 μA/V2, Vtn = 0.4 V, 1/λn = 100 V, W = 160 μm and L = 1.6 μm. VDD = 5 V and Rref = 100 kΩ. Figure 3 (i) Calculate the current flowing in the reference resistor Rref. . 30% (ii) Sketch Vo as a function of Vi, indicating the regions of operation of the transistors. 15% (iii) Calculate the small-signal voltage gain vd/vi when M0 and M1 are biased in their saturated regions of operation. 15% (iv) If the DC and small-signal components of Vi and Vo are denoted ViQ, VoQ and vi, vo respectively, what value of voltage ViQ is required to give IDOQ = 45 μA ? To simplify the calculation, you may neglect channel length modulation effects. 20% (v) Calculate the numerical value of the small-signal voltage gain vd/vi when ViQ has the value derived in part (iv). 20%
Refer to the MOSFET in the figure below where VT = 1 V and k = kn′W/L = 4 mA/V2 - for questions (a-c). (a) [CO1] Identify the value of the gate voltage vG and the drain-source current ids. (b) [CO2] Calculate the drain voltage VD. (c) [CO2] Analyze the circuit to find the source voltage Vs. [Use the method of assumed states. ] (d) [CO3] Consider a MOSFET inverter (SR model) with the following circuit parameters: VCC = 10 V, RL = 10 kΩ. Also, for the MOSFET, VT = 1 V and 1 /(kn′Vov ) = 5. Determine a W/L sizing for the MOSFET so that the inverter output of logical 0 can switch OFF the next MOSFET inverter connected to it.
The ac equivalent circuit for an amplifier is shown in the given figure. Assume the capacitors have infinite value, RI = 170 kΩ, RG = 6.7 MΩ, RD = 100 kΩ, and R3 = 130 kΩ. Calculate the input and output resistances for the amplifier if the MOSFET Q-point is (170 μA, 8 V). Assume Kn = 220 μA/V2 and λ = 0.020 V−1. The input and output resistances are, Rin = MΩ Rout = kΩ
The transmission gate of Fig. 18.7 is fabricated in a CMOS process technology for which = 450 μA/V2, = 150 μA/V2, Vtn = |Vtp|, Vt0 = 0.35 V, γ = 0.25 V1/2, 2ϕf = 1.0 V, and VDD = 1 V. Let QN and QP have dimensions (W/L)n = (W/L)p = 130 nm/65 nm. The total capacitance at the output node is 5 fF. Use as many of the results of Example 18.1 as you need. (a) What are the values of VOH and VOL? (b) For the situation in Fig. 18.7(a), find iDN(0), iDP(0), iDN(tPLH), iDP(tPLH), and tPLH. (c) For the situation depicted in Fig. 18.7(b), find iDN(0), iDP(0), iDN(tPHL), iDP(tPHL), and tPHL. At what value of vO will QP turn off? (d) Find tP. (a)
Q4. Consider the CMOS diagram of the logic gate X given in Figure Q4: Figure Q4 i. Determine the logic expression of output F. [6 marks] ii. Hence derive the truth table for the logic gate X. [8 marks] Q5. Consider the CMOS diagram of the logic gate X given in Figure Q4. Derive [10 marks] the truth table for the logic gate X, by showing clearly the status of each transistor.
Q3. The following is a CMOS amplifier. Assume VDD = 5 V, RF = 750 kΩ, RL = 1 MΩ, VInn = 0.5 V, VIp = −0.5 V, kn = 400 μA/V2, and kp′ = 100 μA/V2, λn = λp = 0.02, (W/L)1 = 40 /1, (W/L)2 = 100 /1 a) Find the Q-point ( ID1, VDS1, and ID2, VDS2 ). For this part (a) assume λn = λp = 0. b) Calculate the voltage gain (AV = VO/VI). For this part (b) and parts (c) and (d) assume λn = λp = 0.02 c) Determine the input resistance (Ri). d) Calculate output resistance (Ro).