Problem 5 - An nMOS differential amplifier is shown, where M1 and M2 are identical and Kn = μnCoxW/L = 5 mA/V2, RD = 20 KOhms, Rss = 100 KOhms, λ = 0, and γ = 0. We also have I1 = I2 = 0.1 mA for v1 = v2 = 0. A) Find gm for the transistors. B) Find the Difference and Common-Mode gains, Av = vo/vd and ACM = vo1/vCM. C) Find CMRR of the amplifier in dB.
In the circuit below, it is desired to choose the unknown resistor R at the left such that 2 mA flows through the 1 K resistor at the right. The NMOS have kn′ = 0.15 mA/V2, Vt = 1 V; the PMOS have kp = 0.08 mA/V2, Vt = −1 V. The length L = 1 um in all cases, the widths in microns for each transistor are marked on the diagram. Find the drain currents ID1, ID2, ID3, and ID4, and the required resistor value R.
Given VDD = 1.2 V, CL = 100 fF, and fCLK = 1.5 GHz, KN = 100 uA/V2, and VTn = 0.5 V. (Ignore channel length modulation factor) i) Draw the transistor schematic for implementing logic function F = A+BCD using static CMOS gate. ii) Size the transistors for worst-case pull-up and pull-down with respect to the following inverter shown in the figure below.
For the circuit given in the diagram, with RF = 560 kΩ, R3 = 100 kΩ, kn′ = 100 μA/V2, kp′ = 40 μA/V2, VTHN = 1 V, VTHP = −1 V, VDD = 5 V, (W/L)n = 40/1, (W/L)P = 100/1, λ = 0.02 V−1, C1 = ∞, and C2 = ∞, calculate the voltage gain, input resistance, and output resistance of the circuit.
For the circuit shown in Fig. 4 below, all BJT transistors are in the forward-active region and MOS transistors are in the saturation region. Include small-signal output resistance ro into the answers if necessary. Numeric answers are not necessary. (a) Find small-signal output resistance Ro (i. e. looking into output node vo ) of the amplifier. [10 points] (b) Find the voltage gain vo/vin of the amplifier [Hint: (vo/vx)⋅(vx/vin ), where vx is signal voltage at the gate terminal of M2]. [16 points] (c) If DC voltage VB2 is increased while M4 is still in the saturation region, what is the impact on the voltage gain magnitude |vo/vin | of the amplifier? Provide explanations to your answer. [5 points]
A Common-Source CMOS amplifier is shown. Assume λ1 = 0 , and μpCoxW/L is 8 mA/V2. R1 and RD are both 500 Ω. Vth,p = −0.5 V. Cap is very big. ( 20 pts total) a) What is the value of VDD that supports M1 operate at the edge of saturation region? (10 pts) b) Calculate the value of small signal gain vout /vin at the edge of saturation mode. (10 pts)
Problem 3 The FET has: Vtn = 2 V, λ = 0.05 V−1 and K = 1.0 mA/V2. VDD = 14 V RD = 1.5 kΩ RS = 1 kΩ AND VDS = 4 VFind the value for IDFind the value for VG Show that the FET is in saturation We reduce the value of RD to zero and at the same time increase the value of VG until the FET operates in Triode region with VDS = 5 V again. Determine the value of VG to achieve this.
The small signal equivalent circuit of a MOSFET amplifier at low frequencies is shown below. As a result of the DC bias the transistor has a transconductance value of gm = 4 mA/V. Let Rsig = 0.4 MΩ, RG = 1.5 MΩ, RD = 20 kΩ and RL = 20 kΩ. The three external capacitances have the following values: CC1 = 90 nF, CC2 = 0.4 μF and CS = 7 μF. Determine the value of the low cutoff frequency fL. Note: The dotted line indicates that the two nodes have the same voltage but no physical wire exists between them.
(b) A junior design engineer increased the length (L) of MOSFET to achieve a unity volage gain for the circuit shown in Figure Q1 b. (i) Please explain (ignore body effect), what could be the possible reason [10 Marks] that increasing the transistor length would result in a lower than expect voltage gain (ii) Which other transistor parameter can be changed to achieve the [5 Marks] desired voltage gain of unity?
The given amplifier circit has the following parameters: R1 = 654, R2 = 327, Rs = 20, and RD = 40 kilo-ohms. Determine the voltage gain, input Norton current (In), and output impedance using the Norton equivalent circuit, you may use the following steps:Calculate gm and rds : Utilize the MOSFET parameters to derive gm and rds. Determine Norton Current (In) : Evaluate the short-circuit current when the input voltage source is shorted. Compute Output Impedance (Rout ) : Nullify the input voltage source and calculate the resistance looking into the output. Once In and Rout are obtained, the voltage gain (Av) can be derived as Av = In×Rout . Give the name of the circuit.
Diodes and active components a) (2 pts each) True/false (circle one) a. (TRUE / FALSE) A diode is a pn-junction b. (TRUE / FALSE) A diode is considered ON when VD > Vbias , where VD is the voltage across the diode. c. (TRUE / FALSE) A MOSFET is considered OFF when Vgs > Vthreshold b) (4 points) For the circuit above and using the switch model of the transistor (Rds = 1 Ω), choose the value of the resistor R such that when the transistor is fully on, the LED turns on and only has 10 mA of current flowing through it. Assume that the LED emits light when it has 1.8 V across it. R =
QUESTION 3 This question examines large signal behaviour of transistor circuits (a) Assume that the MOSFET in Figure 3.1 is operating in saturation and is characterised by a threshold voltage, VT = 1 V. Assume that the parameter, K = 1 mA/V2 where the drain-source current in the MOSFET in saturation is given by equation (3.1). iDS(sat) = K2(vGS−VT)2 Show that the gate-source voltage, vGS, for the circuit shown in Figure 3.1 may be written in terms of the input voltage, vIN, and the output voltage vO, by equation ( 3.2 ): vGS = vINR2 R1+R2 + vOR1 R1+R2 Figure 3.1 (b) For the circuit shown in Figure 3.1, calculate the minimum possible value of output voltage, vO when vIN = 5 V assuming that the MOSFET is maintained in saturation. Assume Rl = R2 = 10 kΩ, and RL = 1 kΩ (c) For the circuit shown in Figure 3.1, determine the value of the constant voltage source, VS, if vO = 4 V when vIN = 5 V and all other circuit parameters are as descirbed in Q3, part (b).
Consider the open-loop circuit (on the left) and closed-loop circuit (on the right) shown in Figure 1 below. In this problem, the open-loop circuit (on the left) will be used to analyze the open-loop behavior of the closed-loop circuit (on the right). closed - loof ciruit Figure 1. Open-loop (left) and closed-loop (right) circuits for Problem 1. Here are the problem parameters:The NMOS devices have gmn = 6 mA/V and rdsn = 25 kΩ. The PMOS devices have gmp = 3 mA/V and rdsp = 15 kΩ. Resistor values are R1 = 1 kΩ and R2 = 3 kΩ. a) Referring to the open-loop circuit of Figure 1, determine the numerical open-loop gain Av. OL = Vout /Vin . For the purposes of this analysis, as we have done a million times before (reminder: this is the 2 nd semester of electronics, so this should not be your first electronics rodeo), you should deactivate all sources in the circuit, except Vin. . b) Referring to the open-loop circuit of Figure 1, determine the numerical open-loop output resistance Rout, oL. , i. e. , the resistance seen looking in at the output node Vout. . You should deactivate all sources in the circuit; feel free to add an appropriate test source(s), if you think you need to do that. c) Referring to the open-loop circuit of Figure 1, determine the numerical loop gain from the test source to the output node: LG = |Vout /Vtest | For the purposes of this analysis, you should deactivate all sources in the circuit, except Vtest. . Also, note that the way the loop gain is defined, it will be a positive-valued quantity. Explain why we want to use a positive loop gain for determining the closed-loop performance [see, e. g. , parts (d) and (e) below]. Your answer for this part should be both i) specific to this problem and ii) generalized to any closed-loop circuit with negative feedback. You are strongly encouraged to consider incorporating a generalized block diagram to help strengthen your argument(s). d) Referring to the closed-loop circuit of Figure 1, determine the numerical closed-loop gain Av, CL = Vout /Vin . Rather than solving the closed-loop circuit of Figure 1 directly for the closed-loop gain, you should instead utilize the results of the previous parts to determine Av, cL. Here, I need to remind you that you should do as you have been (hopefully) doing on the previous parts: first, state the equation you will use to determine Av, cL in terms of, e. g. , Av. ol. and/or Rout, ol and/or LG (i. e. , resist the temptation to dive straight into the numerical values, but feel free to write your equation in terms of Av, ol and/or Rout, ol. and/or LG instead of gmn, gmp, rdsn, rdpp , R1, R2 ), and then plug the numbers in to your equation, and then box your numerical answer along with all the things that we have expected of your numerical quantities since day one. Make it really easy for me to find the equation you used (same story for all of the parts of this problem). e) Referring to the closed-loop circuit of Figure 1, determine the numerical closed-loop output resistance Rout, CL. Rather than solving the closed-loop circuit of Figure 1 directly for the closed-loop output resistance, you should instead follow the same guidance that was given for part (d) of this problem.
VDD = 5 V, Vtn = 0.7 V, μnCox = 75 μA/V2, Vtp = −0.7 V, μpCox = 30 μA/V2, (W/L)1 = (W/L)3 = 3, (W/L)2 = (W/L)4 = 6, (W/L)5 = (W/L)6 = (W/L)7 = (W/L)8 is given for the circuit shown below. a) Give the truth table of the circuit shown below. Explain how the circuit works. b) Calculate the minimum value of (W/L) s so that the switching of the Q′ output from "1" to " 0 " occurs at 2.6 V. Explain your solution. c) Explain how you find the propagation delay tPHL.