Can you find a value for vIN such that NMOS and PMOS would be in Saturation simultaneously? YES or NO? Circle one What is this value for vIN ? Answer: Give step by step derivation and calculation 3. Is this value unique? YES or NO? Circle one Recall for low input the PMOS in Triode and for high input in Saturation. With this in mind, fill in the Table below. INSERT PAGES SHOWING DETAILED WORK. give a point plot of vOUT vs vIN on graph paper on next page Type equation here. For States use C for cutoff, T for Triode, and S for saturation VDD = 6 V, Kn = 0.8 mA/V2, Vtn = 1.0 V, λn = 0.0, Kp = 0.45 mA/V2, |Vtp| = 1.5 V |λp| = 0.
Consider the amplifier circuit shown in the figure below. The transistor has gm = 5 mA/V. The value of the small signal voltage gain vout /vin. Assume capacitor has infinite value and λ = 0. (A) 25 V/V (B) 7.14 V/V (C) −7.14 V/V (D) 0.14 V/V
The MOSFET in the amplifier circuit in Figure 1 below has kn′W/L = 800 μA/V2 and Vt = 0,5 V. Analyse the dc bias circuit to determine ID, VS and VGS assuming λ = 0. Identify this amplifier configuration, draw an appropriate small-signal equivalent circuit diagram of this amplifier and hence calculate the overall signal voltage gain Avs = vo/vsig assuming λ = 0 Figure 1
The following circuit is a discrete common source n- MOSFET amplifier. Assume the transconductance (gm) of the amplifier is 0.5 mA/V. Rsig = 200 Ω, RG1 = 180 kΩ, RG2 = 45 kΩ, RD = RL = 40 kΩ, CC1 = 22 nF and CL = 3 nF (a) Draw a small signal circuit of the amplifier. (b) Derive a transfer function, T(s). (c) Sketch a Bode plot of magnitude. (d) Determine the values of mid-band voltage gain (AM), break frequencies and Bandwidth from the transfer functions in part (b). Q1: n-MOSFET
Given a symmetrical inverter on the left. The transistors are sized in the circuit to the right for worst-case pull-up and pull-down that match the current drive of the inverter. In the PDN, find the Width of NMOS with gate connected to D? So the N2 in the below figure will be equal to
"n" NMOS pass transistors are placed in series as shown, making the delay from point x to y large. (a) Why is the delay from point x to y long? Write an expression for the delay assuming that every NMOS pass transistor has an ON resistance of Ron and a junction capacitance of Ci In order to reduce the delay from point x to y, buffers are inserted along the NMOS pass transistor chain as shown (b) Explain qualitatively, why does inserting buffers cause the delay from point x to y to reduce. (c) Assume that you place a buffer every "m" pass transistors. Also, assume that the delay of each buffer is tbuff. Write an expression for the new delay from point x to y. Explain mathematically why does inserting buffers cause the delay from point x to y to reduce. Finally, explain how you can get the moptimum value which causes to delay from x to y to be minimized. Note: The total number of NNOS' pass transistors is still 'n
(25 pt) Prob 2. Implement the logic function Y = (AB+C).D¯ in 18 -nm FinFET CMOS technology. a) Size the transistors so that the output resistance is the same as that of an inverter with nfinn = 2 for the nMOS and nfinp = 3 for the pMOS b) What input combination(s) result in the worst case tpHL and tpLH ?
For the circuit below, assume the MOSFET operates in saturation and is characterized by parameters VTN and KN. a. Draw the equivalent circuit, replacing the MOSFET with its SCS model. b. Find the output operating point ( VO and ID in terms of the input bias VIN ) c. What is VOUT when VIN = 0 ? d. Draw the small-signal model e. Determine the small-signal gain vout/vin . f. Determine the small-signal output resistance g. Determine the small-signal input resistance.
Assume that the MOSFET has the following parameters: Vt = 1 V, K = 0.4 mA/V2 VA = 40 V. It is connected as an amplifier as shown in Figure Q4 and vs is an AC input voltage and vo is the AC output voltage. The DC drain voltage VD is set to be 0 V. Further assume that all the capacitors in the circuit are very large. Figure Q7. (a) Which type of amplifier configuration does the above circuit (3 marks) belong to? What are the electrical properties of this type of amplifier configuration? (b) Show that the MOS transistor operates in the saturation mode. (3 marks) State one electrical characteristic of a saturated MOS transistor. (c) Determine the drain current ID. (10 marks) (d) Design the load resistance RL such that the AC voltage gain vo/vs of (10 marks) the MOSFET amplifier equals -10 . (e) Suppose the amplitude of AC input vs is 0.2 V and the AC voltage (4 marks) gain of the amplifier equals -10. Do we have a distorted AC output waveform?
For the circuit shown in Figure 2, the MOSFET parameters are K = 0.25 mA/V2 and Vto = 1.4 V. (a) Assume the MOSFET is in the saturation region, calculate RD, Rs and VGS where IDQ and VD are given as 0.5 mA and 1 V respectively. (7 marks) (b) Check the assumption, is your assumption correct? You need to provide all calculation steps. (3 marks) (c) Plot output characteristic curve, draw the load-line and plot Q-point. (3 marks) (d) Choose standard resistor values that are closest to the ideal designed values for Rs and RD and calculate VDS, VGS and ID at Q-point. (8 marks) (e) If the standard resistor Rs has ±10% tolerances, determine the maximum and minimum values of IDQ. (4 marks) Figure 2
a. Someone claims he has implemented a static CMOS gate with the circuit shown. Find the problem with this gate (Hint: Fill out the "truth table" for the gate) b. What is the logic function of this gate? c. By adding just one more transistor to the circuit shown above, fix the problem in a?
A silicon-based MOSFET has a square gate 0.53 μm on edge. The insulating silicon oxide layer that separates the gate from the p-type substrate is 0.22 μm thick and has a dielectric constant of 4.5. (a) What is the equivalent gate-substrate capacitance (treating the gate as one plate and the substrate as the other plate)? (b) Approximately how many elementary charges e appear in the gate when there is a gate-source potential difference of 2.9 V ? (a) Number Units (b) Number Units
Consider the amplifier circuit shown below. Assume a transistor current gain of β = 120. The voltage VBB establishes the Q-point, and the voltage vi is a time-varying signal that produces a variation in the base current, which in turn produces a variation in the collector current and hence a variation in the output voltage vo. (a) Determine RB such that VCEQ = 1.6 V. (b) Determine the minimum and maximum input voltages, vi(min) and vi(max) such that the transistor does not enter cutoff or saturation and determine the corresponding output voltages vo(max) and vo(min) at these values of input voltage (c) What is the voltage gain Δvo/Δvi of the amplifier where Δvo ≡ vo(min)−vo(max) and Δvi ≡ vi(max)−vi(min) ? Assume VBE(on) = 0.7 V and VCE(sat) = 0.2 V.
The parameters of the transistors in Figure P10.88 are VTN = 0.6 V, VTP = −0.6 V, kn′ = 100 μA/V2, kp′ = 60 μA/V2, and λn = λp = 0.04 V−1. The width-to-length ratios of M1 and M2 are 25, and those of all other transistors are 50. The value of VGSQ is such that ID1 = 80 μA, and all transistors are biased in the saturation region. Determine the smallsignal voltage gain Av = vo/vi. Figure P10.88
(15 points) In the current-mirror circuits (a) and (b) shown below, all transistors are operating at the same current and have the same VOV and the same VA. Give the output resistance RO for each mirror in terms of IREFF , VOV, and VA. Give the minimum voltage VO each mirror requires to operate properly in terms of Vt and VOV. (a) (b)
Again consider the circuit shown in Figure 10.37 (a). Let V+ = 5 V and R1 = 35 kΩ. Let VEB1(on) = 0.6 V. Neglect dc base currents. The baseemitter area of Q2 is twice that of Q1. The Early voltages are VAN = 120 V and VAP = 80 V. Determine the small-signal voltage gain for (a) RL = ∞ and (b) RL = 250 kΩ. (a) Fiqure 10.37 (a) Simple BJT amplifier
Problem 4 - The circuit shown is a cascod MOS amplifier. The transistors are identical with gm = 2.5 mA/V, I = 200 μA, and VA = 4 V. A) Find the output impedance of the amplifier, Rout. B) Find the amplifier voltage gain Av = Vo/vi. C ) For Vtn = 0.4 V and Vov = 0.2 V find the DC voltages V1 and the lowest DC output voltage Vo, where all the transistors stay in the saturated region.
*14.127. Find the Q-points of the transistors in Fig. P14.127. if VDD = VSS = 7.5 V, IREF = 250 μA, (W/)12 = 4 O1, Kn′ = 50 μA/V2, VTN = 0.75 V, Kp′ = 20 μA/V2, and VTP = −0.75 V. What is the differential-mode voltage gain of the op amp if λ = 0.017 V−1 for both transistor types? What is the offset voltage of the amplifier?
Q7. Find the voltage gain in the circuit below. Assume that all transistors are saturated. The technology parameters are as follows: VTn = −VTp = 0.7 V, kn′ = 110 μA/V2, kp′ = 50 μA/V2, λn = 0.04 V−1, λp = 0.05 V−1.
The following circuit shows a discrete common source n-MOSFET amplifier. The transconductance of the n-channel MOSFET (gm) is 2 mA/V. Rsig = 100 kΩ, RG1 = RG2 = 20 MΩ, RS = RD = RL = 10 kΩ, CB5 = 1 pF, Cgd = 0.2 pF, VA = ∞ (a) Draw a small signal equivalent circuit of the amplifier in low frequency band. (b) Derive a transfer function in low frequency band, TL(s). function in part(b). (d) Draw a small signal equivalent circuit of the amplifier in high frequency band. (e) Find the high corner frequency (ωiH) using an approximation method (time constant method). (10)
The following circuit shows a discrete common source MOSFET amplifier. The MOSFTE is n-channel MOSFET and early voltage (VA) is ∞. The transconductance of the amplifier (gmm) is 3 mA/V. The frequency responses of the amplifier are as follows. i) The three low break frequencies fL1 = 3 Hz (caused by CC1 ), fL2 = 50 Hz (caused by CS ), fL3 = 10 Hz (caused by CC2 ) ii) High 3 dB frequency, fH = 30 kHz iii) The MOSFET unity gain frequency fT = 100 MHz (a) Draw small signal equivalent circuit of the amplifier in low frequency band and derive transfer function, TL(s). Find mid-band gain (AM) and values of CC1, CC2 and Cs from the transfer function.
(20 points) The cascode current source shown below utilizes two identical PMOS transistors with VDD = 1.8 V, Vtp = −0.5 V, VA′ = −6 V/μm, and μpCox = 100 μA/V2. Design the circuit to obtain I = 50 μA and Ro = 1 MΩ and to allow for the maximum possible voltage swing at the output terminal of the current source. Utilize |Vov| = 0.2 V. (a) Specify the required values of the dc bias voltages VG1 and VG2. [ 5 points] (b) What is the maximum allowable voltage at the output? [5 points] (c) Specify the values of W/L and L for Q1 and Q2. [10 points ]
Ex 4.2: For the circuit shown in Figure 4.1, VDD = 3.3 V and RD = 10 kΩ. The transistor parameters are VTN = 0.4 V, kn′ = 100 μA/V2, W/L = 50, and λ = 0.025 V−1. Assume the transistor is biased such that IDQ = 0.25 mA. (a) Verify that the transistor is biased in the saturation region. (b) Determine the small-signal parameters gm and ro. (c) Determine the small-signal voltage gain. (Ans. (a) VGSQ = 0.716 V and VDSQ = 0.8 V so that VDS > VDS (sat); (b) gm = 1.58 mA/V, ro = 160 kΩ; (c) -14.9) Figure 4.1 NMOS common-source circuit with time-varying signal source in series with gate dc source