In the following circuit R1 = R2 = 1 kΩ, the threshold voltage for forward bias is 0, 7 V, and the dynamic resistance of the diode is 0 Ω. What is the value of the output voltage UOUT when the VIN = −5 V ? (A) VOUT = −5 V (B) VOUT = 0∨ (C) VOUT = −0, 7 V (D) VOUT = −2,5 V (E) VOUT = −1,8 V
The NMOS transistor in the circuit of fig. 1 is to be designed to operate as a resistor. Consider a process technology for which Lmin = 0.5 μm, tox = 10 nm, μn = 500 cm2 /V⋅s. The NMOS has Vtn = 0.8 V and kn = kn′(W/L) = 1.2 mA/V2. a) (04) Find Cox and kn. (ϵox = 3.45×10−11 F/m). Then, determine W for L = 1 um. b) (02) What should be the operating region of the transistor? Explain the reason. c) (14) Calculate VD and ID. Check the operating region of the nmos. d) (05) Calculate the effective resistance between drain and source at this operating point. Fig. 1.
Consider the OP AMP based circuit shown in the figure. Ignore the conduction drops of diodes D1 and D2. All the components are ideal and the breakdown voltage of the Zener is 5 V. Which of the following statements is true? (a) The maximum and minimum values of the output voltage VO are +15 V and −10 V, respectively. (b) The maximum and minimum values of the output voltage VO are +5 V and −15 V, respectively. (c) The maximum and minimum values of the output voltage VO are +10 V and −5 V, respectively. (d) The maximum and minimum values of the output voltage VO are +5 V and −10 V, respectively.
A transistor is used as a switch and the waveforms are shown below. The parameters are given as follows: VCC = 100 V, VBE( (sat) = 4 V, IBS = 10 A, VCE( sat ) = 2 V, ICS = 50 A, td = 0.4 μs, tr = 1.6 μs, ts = 3 μs, tf = 4 μs, tn = 38 μs, t0 = 53 μs and fs = 10 KHz, k = 40% and ICEO = 2 mA. The average losses during the delay time td = mW
In the given circuit, the BJT has a base-emitter ON voltage of 0.7 V, a base-collector ON voltage of 0.5 V and β = 50. Assume that the load is a lamp. The circuit is supposed to switch the lamp ON or OFF based on a digital control signal ( Vcontrol , see figure). Answer the following questions with full details. a) The maximum possible voltage across the lamp is (circle one) (a) +8 V (b) +7.8 V (c) +7.5 V (d) +5 V (e) +4.3 V. Explain: b) What are the values of Vcontrol and Icontrol to achieve the voltage in part (a)? c) Show that the minimum lamp resistance to achieve the voltage in part (a) is about 36 Ω. d) If the lamp resistance is 50 Ω, what is the maximum power consumed by the lamp? e) If the lamp resistance is 15 Ω, what is the maximum power consumed by the lamp?
We wish to design the source follower shown in the right for a voltage gain of 0.8 . If W/L = 30 /0.18 and λ = 0, determine the required gate bias voltage. Assume μnCox = 200 μA/V2 and VTH = 0.4 V(4p)
Given the circuit, assume that the transconductance curve of FETs Q1 and Q2 follows the equation: ID = IDSS(1 − VGS/4)2 where IDSS = 4×10−3 A. Answer the following questions: (a) Determine the drain current ID and drain-to-source voltage VDS for FET Q1 and Q2. (b) Determine the source resistance rs of FET Q1. (c) Consider the resistance r0 looking into the drain of FET Q2. Ideally, this resistance approaches infinity, but for this FET, it is given as 10 MΩ. Calculate the voltage gain Av = Vout Vs of the amplifier. (Rs1 = Rs2 = 2 KΩ )
The below BJT common-emitter amplifier with β = 100 is fed with a signal source that has a resistance of 5 kΩ. A load resistor of 5 kΩ is connected to the output of the circuit as shown in the figure. The input resistance of the amplifier is Ri = 2 kΩ and its output resistance is Ro = 5 kΩ. Find the bias current (1), and the small signal parameters. Use VT = 25 mV. If the peak value of Vπ (denoted by V^π ) is to be limited to 5 mV, what are the corresponding peak value of Vsig (denoted by V^sig ) and peak value of V0 (denoted by v^0 ) in presence of the load resistor? Instructions: Use the given input and output resistance values and the equations related to these quantities (from the lecture notes) to find the small signal parameters and the bias current. To find the peak value of vsig, you need to draw the small signal circuit. replace v/with vsig in series with a 5 k resistor. From the signal circuit, find out how Vπ is related to Vsig. Calculate the open loop voltage gain, and use it with the given load resistor value and the voltage amplifier model to find out how V0 is related to Vsig in the presence of the load. You can also solve the signal circuit to find the answer. v^sig = 17.5 mV V^0 = 1.5 V v^0 = 0.4 V
The following single stage differential amplifier circuit is designed for a 0.18 μm CMOS technology. Given: VDD = |VSS| = 1.5 V, |VTH| = 0.5 V, L = 0.36 μm (for all transistors), μCox = 4μCox = 400 μA/V2, and λ = 0.2 a) For a bias current of Ibias = 200 μA and over drive voltage |Vov| = 0.2 V for all transistors, determine the W/L ratios for M1, M2, M3, and M4. (10 points) b) Determine the small signal differential gain vdo/vid for this design. (10 points) Useful formulae: for n-channel MOSFET iDS = K[(vGS − VTH)vDS − 12 vDS2] triode region K = K′(WL) = μCox(WL) iDS = 12 K(vGS − VTH)2(1 + λvDS) saturation region where VA = 1 λ, and VA = VA′L, ro = 1 λID Vow = VGS − VTH overdrive voltage
Given a BJT with a dc current gain of 100 and a single power supply of 5 V, bias it such that the following conditions are satisfied: (i) The BJT is biased in the common-emitter configuration such that IC = 2 mA; (ii) It is overdriven by a factor of 5 ; (iii) the emitter is grounded and (iv) no biasing resistance less than 10 kΩ or greater than 330 kΩ is to be used. [5 marks] [CO1][BTL3]
In the cascode stage of the below figure, take (W/L)1 = 50/0.5, (W/L)2 = 10/0.5, ID1 = 0.5 mA and RD = 1 kΩ. (a) Choose Vb such that M1 is 50 mV away from the triode region. (b) Calculate the small-signal voltage gain. (c) Calculate the maximum output voltage swing. Which device enters the triode region first as Vout falls? Calculate the swing at node X for the maximum output swing obtained below. In the cascode stage of Fig. 3.59, assume that (W/L)1 = 50 /0.5, (W/L)2 = 10 /0.5, ID1 = ID2 = 0.5 mA, and RD = 1 kΩ. (a) Choose Vb such that M1 is 50 mV away from the triode region. (b) Calculate the small-signal voltage gain. (c) Using the value of Vb found in part (a), calculate the maximum output voltage swing. Which device enters the triode region first as Vout falls? (d) Calculate the swing at node X for the maximum output swing obtained above. Figure 3.59 Cascode stage.