Figure 1 shows a differential amplifier with active current mirror load. By using Thevenin equivalent method, determine the small-signal differential gain. Assume that the body effect, γ = 0 and channel-length modulation, λ ≠ 0.
(c) Consider the circuit shown in Figure 3, where v1 = 7 + 0.015sin(2π×100 kHz×t)V and v2 = 7 V. Figure 3: Sensor amplifier circuit. (i) [2 marks] Calculate vo if the amplifier in Figure 3 is ideal with a differential-mode gain, ADM of 45 dB. (ii) [2 marks] When the circuit in Figure 3 is built on a breadboard the output voltage is found to have a DC component of 0.7 V. Calculate the common-mode rejection ratio of the breadboard circuit.
(a) Derive the expression for output current relation systematically of the BJT current source as shown Assume that all the transistors are identical. (4 marks) (b) Draw the small-signal equivalent circuit for the current source as shown (2 marks) (c) Design the circuit by determining the value of R1 and output resistance RO for the current source as shown Assume that the transistors has the parameters, β = 35, VBE1 = VBE2 = VBE3 = VBE( on ) = 0.7 V, VA = 85 V, and IO = IC2 = 15 μA. (4 marks) (d) Design the circuit to determine the (W/L) ratio for the MOSFET current source as shown in and the output resistances RO1 and RO2 of the current source. Assume that all MOSFET are identical and IREF = 1.2 mA. The MOSFET has the parameters kn′ = 0.13 mA/V2, VTN = 1.2 V and λ = 2.5×10−3 /V (5 marks)
Choose the correct answer from the following options (A D). (10 pt) If W L1 = 1 0.18⋅ W L2 = 1 0.18, and λn = λp = 0, (A) M1 in triode region, M2 in triode region (B) M1 in triode region, M2 in saturation region (C)M1 in saturation region, M2 in triode region (D)M1 in saturation region, M2 in saturation region Fig. 1 Apply for all problems Assume μnCox = 200 μA V2, μpCox = 100 μA V2, VTH = 0.5 for NMOS and −0.5 V for PMOS, λn = λp = 0.01. ro = 1 λID
The circuit of Fig. 4 must be designed for a voltage drop of 100 mV across Rs. Assume the impedance of a capacitor is negligible. Fig. 4 (a) Calculate the minimum allowable value of W/L if M1 must remain in saturation. (10 pt) (b) Based on W/L and VG value calculated in (a), what are the required values of R1 and R2 if the input impedance must be 100 kΩ? (10 pt) Apply for all problems Assume μnCox = 200 μA V2, μpCox = 100 μA V2, VTH = 0.5 for NMOS and −0.5 V for PMOS, λn = λp = 0.01. ro = 1 λID
Calculate the voltage gain of the circuit depicted in Fig. 6. Assume λ = 0 and gm,xro,y ≫ 10 (x and y can be any number). (10 pt) Fig. 6 Apply for all problems Assume μnCox = 200 μA V2, μpCox = 100 μA V2, VTH = 0.5 for NMOS and −0.5 V for PMOS, λn = λp = 0.01. ro = 1 λID
Shown in Figure Q2 is a PMOS current mirror with VDD = 1.8 V, Ibias = 150 μA, R = 2 kΩ, and all transistors sized (W/L) = 18 μm/0.2 μm and having the device parameters for the 0.18−μm CMOS process in Appendix I. Figure 3 a. With vo = 1 V, are all transistors in saturation mode? b. What is the maximum voltage that can appear at vo while still keeping all transistors in saturation mode? c. Assuming all transistors are in saturation mode, what is the small-signal output resistance seen looking into the drain of Q4?
Figure 2 shows a NMOS and PMOS current mirror. Figure 2 The process parameters for the NMOS and PMOS transistor are as below: Transconductance Parameter for NMOS, μnCox = 200 μA/V2 Transconductance Parameter for PMOS, μpCox = 50 μA/V2 Threshold voltage for NMOS, VTHN = 0.3 V Threshold voltage for PMOS, |VTHP| = 0.3 V Channel length modulation for NMOS and PMOS, λ = 0.01 Assume the length of the transistor is 1 μm. Determine the width of the transistor M1 and M2 according to the current gain in Figure 2. If VX is 1.3 V, determine the width of transistor M3 and M4. Determine the impedance when looking into node VY.