We wish to design the source follower shown in Fig. 5 for a voltage gain of 0.8 . If W/L = 30/0.18 and λ = 0. (a) Determine the required gate bias voltage. (10 pt) Fig. 5 (b) Draw Vin vs Vout graph of Fig. 5 . There is no need to specify a specific number; rough behavior alone is sufficient for scoring. (10 pt) Apply for all problems Assume μnCox = 200 μA V2, μpCox = 100 μA V2, VTH = 0.5 for NMOS and −0.5 V for PMOS, λn = λp = 0.01. ro = 1 λID
NOTE: For all the problems here, and from now on, we'll use the common terminology for K. Namely, we'll use Kn = Kn ' (W/L) for n−MOSFETs and Kp = Kp′(W/L) for p-MOSFETs. Kn′ = μnCox and Kp′ = μpCox. For the CMOS inverter circuit shown below, assume the following: Kn′ = Kp′, Ln = Lp = 1 μm, and /VTP/ = VTN = VT. Let's define the threshold as the point (vI = VTH) in the vO versus vI transfer curve where vO = VDD/2. a) Sketch the inverter transfer curve and mark the VTH point. b) Find an expression for the inverter threshold voltage VTH in terms of VDD, VT, Wn and Wp. c) If Wn = Wp, what is VTH ? In what mode of operation are M1 and M2 when VI = VTH ? What about when VI < VTH ?