Electrical Engineering Archive: Questions from 2024-06-2

QUESTION 11: Consider the basic two-transistor NMOS current source shown in the following figure. The circuit parameters are V+ = 5 V, V− = −5 V, and IREF = 217 μA. The transistor parameters are VTN = 1.0 V, kn′ = 80 μA/V2, and λ = 14×10−3 V−1. For (W/L)1 = (W/L)2 = 3, calculate IO for VDS2 = 3.2 V. VGS(V) Format : 9.7562 RO(kΩ) Format : 765.9257 △IO(μA) Format : 9.6594875803085 IO at required VDS2(μA) Format : 553.8432

QUESTION 2: A class-A emitter follower biased with a constant current source is shown below. Assume circuit parameters of V+ = 15 V, V− = −15 V, and RL = 51 Ω. The transistor parameters are β = 47 and VBE(on) = 0.71 V. The minimum current in Q1 is to be iE1(min) = 0.079 A and the minimum collector-emitter voltage is to be vCE(min) = 0.65 V. Determine the value of R that will produce the maximum possible output voltage swing. What is the value of IQ ? What are the maximum and minimum values of iE1 ? Then calculate η, the power conversion efficiency.

QUESTION 6: Refer to the ideal non-inverting op-amp circuit in Figure P9.45. Find v2 and vO for vI1 = 1.51 V and vI2 = 0.16 V. v2(V) Format : 0.63258333929587 v0(V) Format : 2.5325559233922 Figure P9.45

QUESTION 19: The differential amplifier in Figure P11.64 has a pair of PMOS transistors as input devices and a pair of NMOS transistors connected as an active load. The circuit is biased with IQ = 0.68 mA, and the transistor parameters are: Kn = 0.33 mA/V2, Kp = 0.11 mA/V2, λn = 8 mV−1, λp = 15 mV−1, VTN = 1.11 V, and VTP = −1.11 V. (a) Determine the quiescent drain-to-source voltage in each transistor. (b) Find the open-circuit differential-mode voltage gain. VSD1(V) Format : 2.425052706943 VSD2(V) Format : 5.373043205536 VDS3(V) Format : 4.4890649765977 VDS4(V) Format: 8.5370484648972 Ad Format : 89.670985595823 Figure P11.64

QUESTION 7: Figure 13.11 shows the ac equivalent circuit of the gain stage of 741 op-amp. Gain for the gain stage (i.e. Av2) can be calculated using equation given below the Figure 13.11. Given that βn = 200, R8 = 0 Ω, Ri3 = 4.5 MΩ, Ract2 = 71.454090746695 kΩ, and bias current IC17 = 0.69975 mA. Calculate the gain of the gain stage (i.e. AV2). Ri2(MΩ) Format : 2.2947457985556 R017(kΩ) Format : 52.558070797438 AV2(V/V) Format: -977.58272576696 Figure 13.11 Av2 = vo2 vo1 = −βn(1 + βn)R9(Ract2∥Ri3∥Ro17) Ri2{R9 + [rπ17 + (1 + βn)R8]}

QUESTION 5: Consider the differential amplifier in Figure P11.17 with parameters V+ = 4 V, V− = −4 V, and IO = 1.3 mA. Neglect base currents and assume VA = ∞ for all transistors. The emitter currents can be written as IE1 = IS1 EXP(VBE1/VT) and IE2 = IS2 EXP(VBE2/VT). If v1 = v2 = 0, IS1 = 3.9×10−15 A and IS2 = 2.4×10−15 A, determine (vO1 − vO2) for RC1 = 7.5 kΩ and RC2 = 7.6 kΩ. IE1 (mA) Format : 0.4062 IE2 (mA) Format: 0.7433 (vO1 − vO2) (V) Format : -8.7625 Figure Pl1.17

QUESTION 20: The output stage in the following Figure is a Darlington pair emitter-follower configuration. Assume β = 230 for all npn transistors and β = 80 for all pnp transistors. Let VA7 = 85 V for Q7, VA11 = 192 V for Q11, and VA = ∞ for all other transistors. Calculate the small-signal resistance looking into the emitters of Q9 and Q8, i.e. Re9 and Re8, respectively. Hence, determine the output resistance R0. Re9 (kΩ) Re8 (Ω) Format : 8.23 RO (Ω) Format : 33.37 Format : 8.23 Re8 (Ω) Format: 33.37 RO (Ω) Format : 88.45

QUESTION 6: Consider the output stage in Figure 13.8. Assume the reverse saturation currents for Q18 and Q19 are IS = 10−14 A, and the reverse saturation currents for Q14 and Q20 are IS = 3×10−14 A. Note that Q13A is 1/4 area of Q12. Neglect base currents except when you are calculating IE18. Given that β = 191 and IREF = 0.298 mA. By first assuming that VBE19 = 0.6 V, calculate the bias currents for Q13A, Q18 and Q19. Calculate also the bias voltage VBB, and the bias currents for Q14 and Q20. Hints: You may refer to Example 13.3 in the textbook. IC13A (mA) Format : 0.0967 IC18 (μA) Format : 43.94676894093 IC19 (mA) Format: 0.0535 VBB (V) Format: 3.7203443524428 IC14 (μA) Format: 72.626056695569 IC20 (μA) Format : 63.975062486445 Figure 13.8: Basic output stage of 741 op-amp

QUESTION 3: Figure 13.10 shows AC equivalent circuit for 741 Input Stage. Given that β = 200, VA = 50 V, IC1 = 8.9 μA, R2 = 2 kΩ, and Ri2 = 3.231 MΩ find Ad = v01/vd = −gm2(ro4∥Ract1∥Ri2). gm2 (mA/V) ro4 (MΩ) Format: 0.33520245450558 Ract1 (MΩ). 9396528790963 Ad(V/V) Format : 6.3840508097726 Format : −556.6752944579 Format : 0.33520245450558 ro4 (MΩ ) Format : 5.9396528790963 Ract1 (MΩ ) Format: 6.3840508097726 Ad (V/V) Format : -556.6752944579 Figure 13.10

a) Design the current switch (Emitter-Coupled Pair) shown in the figure below (Find the values of R1 and RC ) for vC1 = −1.4 V and vC2 = −0.8 V, VI = −1.6 V, IEE = 1 mA and VREF = −2.2 V.

Consider the differential amplifier shown in Figure1 with transistor parameters β = 150, VBE(on) = 0.7 V, and VA = ∞. (a) Design the circuit such that the Q-point values are IC1 = IC2 = 100 μA and vo1 = vo2 = 1.2 V for v1 = v2 = 0. (b) What are the maximum and minimum values of the common-mode input voltage? Figure 1

Problem 3: Calculate the dc characteristics of a MOSFET diff-amp shown in Figure. The transistor parameters are: Kn1 = Kn2 = 0.1 mA/V2, Kn3 = Kn4 = 0.3 mA/V2, and for all transistors, λ = 0, and VTN = 1 V. (a) Determine the maximum range of common-mode input voltage. (b) Determine the differential-mode voltage gain, common-mode voltage gain, and CMRR. Assume λ = 0.01 V−1 for M4.

a) Compute differential-mode gain (Adm), for output taken differentially. Assume there is no body/bulk effect and ro is ∞. (10 pts) b) Convert the circuit into a common-mode half circuit. (5 pts) c) Compute common-mode gain (Acm), for output taken differentially. Assume there is no body/bulk effect and ro is ∞. (5 pts)

For a prototype OpAmp below (differential amplifier cascaded with Common-emitter and Common-Drain), given VDD = 5 V, −VSS = −5 V, IREF = 0.8 mA, (W/L)1 = (W/L)5 = 5. design requires IO2 = 1.1 mA, IO3 = 2 mA, IO4 = 10 mA, assume all MOSFET transistors have λ = 0.02/V, and given gm2 = gm6 = gm7 = gm8 = 5 mS, gm9 = 1.1 ms. For MOSFET ro = (1/λ + |VDS|)/IDS At quiesent condition (v1 = v2 = vo = 0), VGS1 = VGS2 ≅ 2 V, Vds6 ≅ 3 V, Vds3 ≅ 6 V, and Vds4 = 5 V. For PNP transistor Q12, assume |VBE| ≅ 0.7 V, β = 100, VA = 50 V. Determine the CMRR for the OpAmp in dB if RD = 0.9 Kohm, rpi12 = 1.2 Kohm, ro8 = 56 Kohm, ro6 = 22 Kohm, ro2 = 27 Kohm.

QUESTION 14: The parameter for the circuit in Figure 10.17 are V+ = +5 V and V- = 0 V. The transistor parameters are VTN = 0.7 V, kn′ = 74 μA/V2, and λ = 28×10−3 V−1. The transistor width-to-length ratios are (W/L)1 = 23, (W/L)2 = 13, and (W/L)3 = 3. Find VGS1 voltage. Then, determine IREF and IO at VDS2 = 2.5 V. VGS1 = VGS2(V) Format: 6.269 IREF(μA) Format : 547.3383 Original IO at VGS1(μA) Format : 789.8504 RO at VGS1(kΩ) Format : 67.7883 Change in IO(μA) Format: 50.784027979257 IO at required VDS2(μA) Format: 379.8239 Figure 10.17

QUESTION 10: The circuit parameters for diff-amp shown in Figure 11.30 are V+ = 6 V, V− = −6 V, and IQ = 0.52 mA. The transistor parameters are β = 66, VA1 = VA2 = 105 V, VA3 = VA4 = 75 V, and VA5 = ∞. Determine the open-circuit differential-mode voltage gain. What is the output resistance of the diff-amp? Find the value of load resistance RL that reduces the differential-mode gain to 74 percent of the open-circuit value. Ad (open circuit) Format : 4622.5359058583 Ro(kΩ) Format : 782.54629054754 RL(kΩ) Format : 948.8308389362 Figure 11.30

QUESTION 19: The differential amplifier in Figure P11.64 has a pair of PMOS transistors as input devices and a pair of NMOS transistors connected as an active load. The circuit is biased with IQ = 0.84 mA, and the transistor parameters are: Kn = 0.37 mA/V2, Kp = 0.12 mA/V2, λn = 8 mV−1, λp = 19 mV−1, VTN = 1.48 V, and VTP = −1.48 V. (a) Determine the quiescent drain-to-source voltage in each transistor. (b) Find the open-circuit differential-mode voltage gain. VSD1 (V) Format : 4.7039047822905 VSD2 (V) Format : 8.3026036628505 VDS3 (V) Format : 2.3423479083074 VDS4 (V) Format :2.8658923084038 Ad Format :27.7556360535 Figure P11.64

QUESTION 8: The transistor parameters for the circuit shown in Figure P11.29 are β = 150, VBE( on ) = 0.7 V (except for Q4), VA = ∞ for Q1 and Q2, and VA = 145 V for Q3 and Q4. Earlier dc analysis yields quiescent values I1 = 0.5 mA and IQ = 140 μA. (a) Determine the common-mode input resistance, Ricm. (b) For RC = 75 kΩ, determine the common-mode voltage gain, Acm. rπ1 (kΩ) Format : 99.88 R2 (kΩ) Format : 0.5755 ro4 (MΩ) Format : 2.086 gm4 (mA/V) Format : 5.2938 Ricm (MΩ) Format : 276.7 Acm Format : −0.0383 Format : -0.0383 Figure P11.29

QUESTION 4: Refer to Figure 13.11 that shows the ac equivalent circuit of the gain stage of 741 op-amp. Given that β = 200 and IC17 = 0.6705 mA. Find input resistance of the gain stage (i.e. Ri2) when R8 = 0 Ω. IC16 (μA) Format : 88.4759 rπ16 (kΩ) Format : 867.6090708423 rπ17 (kΩ) Format : 3.7294032856343 Ri2 (MΩ) Format :3.9224798448834 Figure 13.11

QUESTION 5: Consider the differential amplifier in Figure P11.17 with parameters V+ = 7 V, V- = −7 V, and IO = 0.6 mA. Neglect base currents and assume VA = ∞ for all transistors. The emitter currents can be written as IE1 = IS1 EXP⁡(VBE1/VT) and IE2 = IS2 EXP⁡(VBE2/VT). If v1 = v2 = 0, IS1 = 3.3×10−15 A and IS2 = 2×10−15 A, determine (vO1 − vO2) for RC1 = 7.6 kΩ and RC2 = 8.2 kΩ. IE1 (mA) Format: 0.9563 IE2 (mA) Format : 0.3989 (vO1 − vO2)(V) Format : -0.3788 Figure P11.17

QUESTION 14: The bias voltages in the diff-amp shown in Figure P11.31 are changed to V+ = 7 V and V− = −7 V. The transistor parameters are Kn1 = Kn2 = 100 mA/V2, Kn3 = Kn4 = 190 mA/V2, λ1 = λ2 = 0, λ3 = λ4 = 14 mV−1 and VTN = 0.3 V (all transistors). Design the circuit such that VDS1 = VDS2 = 4 V and ID1 = ID2 = 67 μA when v1 = v2 = −1.15 V. Calculate the change in IQ if v1 = v2 = +1.15 V. RD (kΩ) Format : 99.602524478406 R1 (kΩ) Format : 702.07048099988 δIQ (μA) Format : 4.9266 Figure P11.31

QUESTION 23: For the transistors in the circuit in Figure P11.3, the small-signal parameters are: gm2 = 390 μA/V, gm3 = 430 μA/V, ro1 = ro2 = ro3 = ∞, and ro4 = ro5 = 130 kΩ. (a) Determine the differential-mode voltage gain, Ad = vo3/vd and the common-mode voltage gain, Acm = vo3/vcm. (b) Determine the output voltage vo3 if v1 = 2.14 sin⁡ωt V and v2 = 1.88 sin⁡ωt V. Ad Format : -9.2696350295674 Acm Format : 0.048325068945492 vo3 (sin⁡ωt V) Format : -0.62598263866787 Figure P11.3

QUESTION 7: Figure 13.11 shows the ac equivalent circuit of the gain stage of 741 op-amp. Gain for the gain stage (i. e. Av2) can be calculated using equation given below the Figure 13.11. Given that βn = 200, R8 = 0 Ω, Ri3 = 4.5 MΩ, Ract2 = 74.404761904762 kΩ, and bias current IC17 = 0.672 mA. Calculate the gain of the gain stage (i.e. Av2). Ri2(MΩ) Format : 7.2795939423957 Ro17 (kΩ) Format : 76.708475809295 Av2 (V/V) Format : −765.70604502993 Format: 7.2795939423957 Ro17 (kΩ) Format : 76.708475809295 Av2 (V/V) Format : -765.70604502993 Figure 13.11 Av2 = vo2 vo1 = −βn(1 + βn)R9(Ract2∥Ri3∥Ro17) Ri2{R9 + [rπ17 + (1 + βn)R8]}

QUESTION 13: Consider power supplies for the diff-amp shown in Figure P11.46 are V+ = 8 V and V− = −8 V. The transistor parameters are Kn1 = Kn2 = 70 μA/V2. Let λ1 = λ2 = 0 mV−1 and VTN = 0.5 V. Ad Format: 5.232606457505 Acm Format : -0.84630587769593 CMRRdB (dB) Format: 44.789943584578 Figure P11.46

A MOSFET is fabricated with the work function difference ϕMS = −0.46 V, the fixed charge QF/q = 2×1011 /cm2, the mobile charge QM = 0, and the interface charge QIT = 0, the oxide thickness xo = 0.05 μm, the gate area AG = 10−3 cm2, and the substrate doping concentration ND = 1015 /cm3. QI/q = 4×1011 /cm2 is the ion charge implanted immediately adjacent to the Si−SiO2 interface to adjust the threshold voltage VT. (a) Determine VFB. (b) Determine VT. (c) Is the given MOSFET an enhancement mode or depletion mode device? Explain.

Given a depletion-type MOSFET with IDSS = 6 mA and VP = −3 V, determine the drain current at VGS = −1, 0, 1, and 2 V. Compare the difference in current levels between −1 V and 0 V with the difference between 1 V and 2 V. In the positive VGS region, does the drain current increase at a significantly higher rate than for negative values? Does the ID curve become more and more vertical with increasing positive values of VGS? Is there a linear or a nonlinear relationship between ID and VGS ? Explain.

Problem 1. Figure shows a variation of the feedback-bias circuit. Using a 1.8−V supply with an NMOS transistor for which Vth = 0.3 V, μnCoxw L = 8 mAV2, and λ = 0, provide a design that biases the transistor at ID = 1 mA, with VDS large enough to allow saturation operation for a 0.7−V negative signal swing at the drain. Use 1 M-Ohm as the largest resistor in the feedback-bias network. What values of RS, RD, RG1, and RG2 have you chosen? Specify all resistors to two significant digits.

In this question we will consider feedback. Let R1 = 9 kΩ and R2 = 1 kΩ. CB is a big capacitor (open at DC and short at AC). (70 pt) a) What is the feedback type? What is the feedback factor f? (10 pt) b) Ignoring feedback loading (ignore R1 and R2), what is the open loop gain a, loop gain T and closed loop gain ACL? (30 pt) c) Ignoring feedback loading What is the output resistance of the OPAMP and feedback? (10 pt) d) Repeat steps b) and c) without ignoring feedback loading (i. e add R1+R2 load at the output) (20 pt)

Consider the following circuit Inverter timing: Propagation delay tp = 20 pS Flip-Flop timing: Setup time tsu = 30 pS Hold time thold = 10 ps Clock-to-Q delay tclk- = 50 pS Assume the CLK signal has a square waveform with 50% duty cycle. a. Draw the waveforms of signals CLK, D, and Q for 4 clock cycles. b. What is the ratio between the oscillation frequency of the signals CLK and Q ? c. For this circuit to operate correctly, determine the maximum CLK frequency based on the given timing characteristics of the flip-flop and the inverter. d. Would a hold time violation occur on the flip-flop at any CLK frequency? Why or why not? e. If this circuit dissipates 100 Micro-Watts when operating at Vdd = 2.5 Volts and CLK frequency of 1 GHz, estimate the power dissipation of the circuit when operating at Vdd = 1.25 V and CLK frequency of 100 MHz. Assume the power dissipation is dominated by the switching (dynamic) power. (1 GHz = 109 Hz and 1 MHz = 106 Hz)

For the BICMOS amplifier shown below; the BJT parameters are β = 100, |VBE| = 0.7. The NMOS transistor's parameters are |Vt| = 1 V, k = 2 mAV2, a) Find the DC collector current for Q1 (neglect the base current, i.e. IE ≈ IC) and the DC drain current for M1 b) Find the voltage gain, input resistance, and output resistance

A MOSFET amplifier, as shown, has no input current on the control pin. It is configured to operate as an analog circuit and provide 3 A to the load. What is the power lost in the MOSFET, and what is the circuit's efficiency? Hint: If the load current is 3 A, and it's constant, then what's the load voltage? Then calculate the transistor voltage and loss. The same amplifier is now configured as a PWM-driven circuit. When the MOSFET is "on", the voltage across the MOSFET is 0.1 V, and when it is "off", the current is 0 A. The average load current is the same as in part 1. Find. . . a. (1 point) The control duty cycle. b. (2 points) The power in the MOSFET when it is on. c. (2 points) The average power lost in the MOSFET. d. (1 point) Estimate. . . is the circuit more or less than 90% efficient? DO NOT DO ANY DETAILED MATH!

Figure 2 shows C-V plots of three MOS-C devices with the same doping but different oxide layer thicknesses ' do′ Figure 2: C-V plots for three MOS-C devices labeled as A, B and C. (1) The MOS-C devices correspond to. (2 points) (a) n-type MOS-C (b) p-type MOS-C (2) What are the bias conditions of points 1, 2, and 3? (Write the point number in front of the correct options below) (3 points) Accumulation : Inversion (low f) : Inversion (high f): Flat band : (3) Which device has the largest 'do′ ? (3 points) (a) A (b) B (c) C (4) When a MOSFET is biased into inversion and is AC modulated, the carriers in the channel are modulated by (3 points) (a) R-G (b) Carriers from the source and drain region (c) Leakage current from the gate (d) Depletion of the majority in the inversion region

In the circuit below, (W/L)1 = 100, (W/L)2 = 400, ID = 2.5 mA. a. What are the functions of M1 and M2 (i.e., amplifier, topology, current source, or diode-connected load)? b. If λ = 0, RL = ∞, determine the voltage gain Av. c. If λ = 0, RL = 400 Ω, determine the voltage gain Av. d. If λ = 0.1 V−1, RL = 400 Ω, determine the voltage gain Av.

The BJT circuit shown in the figure is fed by a binary input voltage, VBB, which switches between ±0.6 V. a. Draw equivalent circuit with Ebers-Moll model? b. At which mode the transistor is operating at VBB = 0.6 V. Show your simplified circuit for this biasing condition c. At which mode the transistor is operating at VBB = −0.6 V. Show your simplified circuit for this biasing condition d. Calculate the output voltage for VBB = 0.6 V e. Calculate the output voltage for VBB = −0.6 V. Transistor parameters: αFIF0 = αRIR0 = Is = 10−13 Amp, αF = 0.99, αR = 0.01.

The inverting-amplifier circuit shown in Fig. P4.6 uses a resistor Rf to provide feedback from the output terminal to the inverting-input terminal. (a) Use the equivalent-circuit model of Fig. 4-6 to obtain an expression for the closed-loop gain G = vo/vs in terms of RS, Ri, Ro, RL, Rf, and A. (b) Determine the value of G for Rs = 10 Ω, Ri = 10 MΩ, Rf = 1 kΩ, Ro = 50 Ω, RL = 1 kΩ, and A = 106. (c) Simplify the expression for G obtained in (a) by letting A → ∞, Ri → ∞, and Ro → 0 (ideal op-amp model). *(d) Evaluate the approximate expression obtained in (c) and compare the result with the value obtained in (b). Figure P4.6: Circuit for Problem 4.6. Figure 4-6: Equivalent circuit model for an op amp operating in the linear range ( vo ≤ |Vcc| ). Voltages vp, vn, and vo are referenced to ground.

The CMOS transmission gate shown has an input voltage of 2.0 V when it turns off. The W/L of the n-channel is 4 μm/0.6 μm and the W/L of the p-channel is 8 μm/0.6 μm. Estimate the change in output voltage due to clock feedthrough. You may assume the total parasitic capacitance between the output node and ground is 100 fF, that VDD = 3.3 V, and that the clock signal changes very fast. Ignore the changes due to overlap capacitance. Assume, VTN0 = 0.7 V, VTP0 = −0.8 V, Cox = 3.4 fF/m2.

Consider the series-shunt feedback amplifier of Figure below. Assume that the voltage divider (R1, R2) is implemented with a 1-MΩ potentiometer. Assume that the MOSFET is biased so that gm = 4 mA/V and ro is large. Also, RD = 10 kΩ. Find the value of R1 that results in a closed-loop gain of 5 V/V.

For the amplifier with |VGS| − |VTH| = 0.2 V, ro = 100 kΩ (for M1, M2, M3, M4), ro5,6 = ∞, IB = 10 uA, and (W/L)5 = 10⋅(W/L)6, find vo/vi. Assume VB1, VB2, and VB3 are DC voltages.

Figure Q1(b) shows a single-stage amplifier driving a load of RL and CL. VBIAS and IDC are DC bias voltage and current of the transistor Q1, respectively. By considering the internal capacitive effect of Q1, analyse the circuit using high-frequency small-signal model to obtain the pole frequencies of the circuit, assuming the Early effect is neglected. [10 Marks] Figure Q1(b)

Find the drain current in the MOS devices for the following cases 1) (W/L)1 = (W/L)2, 2) (W/L)1 = 2(W/L)2, and 3) (W/L)1 = 4(W/L)2. What should be the values of R1 and R2 such that the devices remain in saturation region in all the three cases. Assume λ = 0.

A differential amplifier connected in the circuit in the given figure has the parameters listed below with RI = 4.5 kΩ and RL = 550 Ω: Input resistance Rid = 0.5 MΩ Output resistance RO = 20 Ω A = 80 dB vi = VI sin⁡ωt Find the overall voltage gain AV, current gain Aj, and power gain AP for the amplifier, and express the results in dB. (Round the final answer to one decimal place.) AV = dB Ai = dB AP = dB

Consider the amplifier circuit in Fig. 4 which amplifies input Vin to output Vout. The circuit accomplishes this by using a bipolar junction transistor or BJT. The BJT is a three-terminal circuit element with nodes B, C, and E. In some situations, the BJT can be modeled with an equivalent linear circuit containing a voltage-dependent current source as shown in Fig. 5. Figure 4: Amplifier circuit with BJT Figure 5: Equivalent circuit model for BJT We want to find the Thevenin and Norton equivalent of the amplifier circuit across the terminals Vout (i. e. , between nodes C and E ). Note: You can use the parallel operator (||) in your final answers. (a) Redraw the original amplifier circuit in Fig. 4 but with the BJT equivalent circuit model in Fig. 5 substituted. (b) Use the open circuit test to find the Thevenin voltage, Vth , between nodes C and E. Recall the open circuit test finds Vout = Voc when an open circuit is connected across the terminals, then Vth = Voc. (c) Use the short circuit test to find the Norton current, Ino, between nodes C and E. Recall the short circuit test finds Iout = Isc when a short circuit is connected between the terminals, then Ino = Isc. (d) Find the Thevenin/Norton resistance Rth = Rno using Rth = Vth Ino. (e) We can also find Rth by turning off all of the independent sources (but not the dependent sources) and deriving the equivalent resistance seen from the terminals. Derive Rth with this method. Does it match your answer from part (c)? Hint: To simplify the dependent source, focus on first finding VBE.

An amplifier (with DC gain = 100 V/V, input resistance of 100 kΩ and output resistance of 1 kΩ ) is capacitively coupled (0.1 μF) to a 10 kΩ source, and it drives a parallel RC load of 1 kΩ and lnF. This is shown in the figure below. a) By inspection, what are the gains at DC and at very high frequency? What type of magnitude response is it (LP, HP or BP)? b) Derive the transfer function VoVs(s) c) Sketch the transfer function. Calculate and show the frequencies (in Hz ) and magnitudes (in dB ) of interest.

Consider the following differential amplifier. Assume all transistors are operating in saturation region and λ = γ = 0, VDD = 3 V, VTH(NMOS) = 0.5 V, μnCox = 1 mA/V2, R = 100 Ω, (W/L)1 = (W/L)2 = 16 and (W/L)0 = 32. Also, assume that the Vbias = 0.75 V and the circuit is symmetric. a) What should the value of RL. be if the magnitude of the differential voltage gain of the circuit is 4 V/V. b) For the circuit to operate properly (i.e., all transistors operate in their saturation region), what are the minimum and maximum values of the input common-mode voltage (i.e., input DC voltage)

Identify the Q-points of the transistors in the amplifier in the figure given below if VDD = 6 V, VSS = 6 V, I1 = 600 μA, I2 = 500 μA, I3 = 2 mA, Kn = 5 mA/V2, VTN = 0.70 V, λn = 0.02 V−1, Kp = 2 mA/V2, VTP = −0.70 V, and λp = 0.015 V−1? What are the differential-mode voltage gain and input resistance and output resistance of the amplifier? (Round the final answer to the nearest whole number. ) The Q-points of the transistors in the given amplifier are (2.00 mA, 5.10 V) (500 μA, 3.89 V) (600 μA, 5.18 V) (300 μA, 5.10 V) (200 μA, 3.48 V) (2.00 mA, 6.00 V) The differential-mode voltage gain and input resistance and output resistance of the given amplifier are Adm = Rid = , Rout = Ω.

Single stage differential amplifier a) Derive the differential-mode transfer function of the differential amplifier shown in Figure 1. Assuming an ideal Op-Amp. b) Design the differential amplifier for a differential gain of 100(Ad = vout vA−vB = vout vd), making R2 = R4, and R1 = R3. c) Assuming that VCC = VEE = 12 V. Simulate circuit to obtain its gain and bandwidth. Plot the common-mode rejection ratio (CMRR) as a function of frequency. Assume that CMRR is defined as CMRR = Ad Acm and use the LM741 Op-Amp. d) Derive the common mode gain transfer function (Acm = vout vcm) assuming that the feedback resistors are not matched: R2 = R4 + 1%. Repeat the simulation for CMRR and plot it vs frequency. Figure 1. Differential Amplifier

Determine the closed-loop gain of each amplifier in Figure 12-65.

For the circuit provided assuming (W/L)1 = 5 design resistor R and all transistor (W/L) s such that: Iref = 25 μA, I2 = 100 μA, I3 = 15 μA, andI5 = 55 μA. Assume saturation operation with the given parameters: kn′ = kp′ = 150 μA/V2 Vtn = |Vtp| = 0.6 Vλn = λp = 0 R = kΩ (W/L)2 = (W/L)3 = (W/L)4 = (W/L)5 =

Consider the amplifier shown below. Assume a supply voltage of 2.5 V, a bias current of 100 μA, a load resistance of 10 kΩ, Vt0 = 500 mV, and kn′ = 50 μA/V2. a) What is the maximum possible small-signal gain? Find the corresponding W/L, V1 and DC operating point (i.e., all node voltages and branch currents) if VoV(min) = 150 mV and W/L(max) = 32. (Note: The W/L ratio is restricted to be an integer. ) b) The second- and higher-order terms in the gain expression are known as distortion. (Obviously, you cannot neglect this in this problem. . . ) Redesign the circuit such that for vi = 50 mV, the distortion term is less than 3.5%. (Hint: Take the ratio of the second-order and linear terms. ) Your circuit must still meet the constraints imposed in part (a). Recalculate the WIL, V1, DC operating point, and small-signal gain.

Feedback low-noise amplifier Consider the amplifier circuit shown in below. Assume the following: M1 and M2 are in saturation. Ignore channel length modulation and the body effect in both transistors. Ignore all parasitic capacitances in M1 and M2. Ignore the flicker noise in M1 and M2. a) Derive the small signal input impedance Zin as a function of RF, RL, and small signal equivalent parameters of M1 and M2. (5 points) b) Derive the small signal voltage gain as a function of RF, RL, and small signal equivalent parameters of M1 and M2 under the input impedance matching condition, i. e. , Zin = Rs, where Rs is the source impedance. (3 points) c) Derive the noise figure of this amplifier under the input impedance matching condition. (17 points)

Figure below shows a circuit suitable for op-amp applications. For all transistors β = 100, VBE = 0.7 V, and ro = ∞. a) For inputs grounded and output held at 0 V (by negative feedback) find the collector currents of all transistors. Neglect base currents. b) Calculate the input resistance. c) Calculate the gain of the amplifier with a load of 5 kΩ. d) With load as in (c) calculate the value of the capacitor C required for a 3-dB frequency of 100 Hz.

Consider the above MOSFET amplifier circuit and assume that the capacitors are infinitely large. MOSFET parameters are given to be: Vt = 0.9 V, kn′ = 80 μA/V2, W = 50 μm and L = 10 μm Component values are given as Rsig = 1.2 KΩ, R1 = 10.6 KΩ, R2 = 12.2 KΩ, VDD = 16 V, VD = 12 V, VDS = 9 V and RL = 8.1 KΩ. Compute the small signal transconductance ( gm ) of the MOSFET in this circuit (express the result in mA/V units).

An instrumentation amplifier is used to provide a differential amplifier for highly sensitive sensors. A designer would like to have an instrumentation amplifier with a differential gain of 9 V/V, i. e. vo = 9∗(v2−v1), and has selected R3 = R4 = 10 kΩ, and R1 = 1 kΩ. What should the resistance of R2 be, in kΩ?

For the shown class AB push pull power amplifier, determine: A. The maximum ideal peak values for the output voltage and current. B. The maximum ideal ac output power and the dc input power of the amplifier. C. The dc parameters VB(Q1), VB(Q2), VE, ICQ, VCEQ(Q1), VCEQ⁡(Q 2). D. The power delivered to the 8 Ω load resistor, given that the i/p is 8V pp. E. The efficiency of the power amplifier. F. The i/p resistance seen by the i/p source Vs? Given that βac = 200. G. The power gain. H. If the 8 V source has an internal resistance of 50 Ω, what is the actual power delivered to the 8 Ω load.

For the amplifier circuits below assume the following transistor parameters NMOS (Vt0 = 0.45, μnCox = 270 μA/V2, γ = 0, λ = 0 ). The Cgs, Cgd, Cdb, and Csb capacitances have been pre-calculated for you and are listed in the figure below. You only need to consider these capacitances in the problem. a. (55 pts) Find the poles of the amplifier below and write the equation for the open loop amplifier gain as a function of frequency, AoL(s). You may ignore all zeros in the response. b. (25 pts) What is the unity gain frequency of the open-loop amplifier, ωta, from part (a)?

Design Parameter VDD = 1.8 V, μnCox = 100 uA/V2, μpCox = 50 uA/V2, λn = 0.1 V−1, λp = 0.2 V−1, VTH, N = 0.4 V, VTH, P = −0.5 V Length = 0.35 um, ID1, 3 = 100 uA, IDREFn 1, 3 = 30 uA, DC voltage of Vin = 1.2 V. Design 1) Design common source amplifier and biasing circuits in the circuit (a) (Determine W/L of transistors and RREF1 and derive the gain) (15 pt) 2) Design common source amplifier and cascode biasing circuits in the circuit (b) (Determine W/L of transistors and RREF2 and derive the gain) (15 pt)

A certain class C amplifier transistor is on for 15% of the A. What is the average power dissipation for maximum output? B. What is the resonant frequency of a LC circuit with L = 15 mH and C = 1.5 μF? C. What is the maximum peak-to-peak output voltage with VCC = +20 V? D. What is the efficiency of the class C amplifier if the equivalent parallel resistance (Rc) in the collector LC circuit is 40 Ω?

Problem 5: Consider the amplifier in the Figure 5. Assume that this particular Field Effect Transistor has a threshold voltage Vto = 5 V and the conduction parameter K = 28 mA/V2. Figure 5 5.1. (10 points): Find the gate-source voltage VGS. 5.2. (10 points): Find the drain-source voltage VDS in the saturation region.

Glenn wants to design a very high gain amplifier while keeping high input resistance but the maximum value of resistors that he has available are of 100 MΩ. He choose following topology for designing high gain amplifiers while keeping high input resistance. a) Design the circuit for Glenn such that input resistance is 10 MΩ and gain of the amplifier is 120 V/V. b) Explain why this topology is better than simple non-inverting amplifier in terms of limitations of input resistance and gain. What caused this circuit to have high input resistance as well as high gain. (Hint: Current through R4 adds up with current from R3)

For the following circuit, given k′n = 96 μA/V2, Vtn = 0.5 V, λ = 0, (W/L) for M1 is 5 and (W/L) for M2 and M3 is 10 , a. Solve for the gate-source voltage of M1 and M2 ( VGS1 on the diagram). b. Determine the required value of resistor R1. c. Determine the drain voltage of M2(VD2 on the diagram). d. Find the largest value of resistor R2 for which M3 will still operate in the saturation region.

Determine the input resistance, voltage gain and output resistance of the CC amplifier shown below if β = 200, RS = 5 kΩ, RL = 500 Ω, and IC = 1 mA. Neglect rb and ro. Do not include RS in calculating the input resistance. In calculating the output resistance, however, include RL. Include both RS and RL in the gain calculation.

E10.16 A bipolar cascode transconductance amplifier is shown in Figure E10.16. Given RS = 1 kΩ, RL = 50 kΩ, CL = 0.1 pF, ISUP = 100 μA and roc→∞, find Iout/Vs at DC and ωMBB . Assume that VBBAS is set such that all devices are operating in their constant-current region. Include Ccs = 50 fF in the calculations.

Q5. Assume the input offset voltage and currents of the op-amp are negligible, and the outputvoltage range of the op amp in Fig. is equal to the power supply voltages. What is the value of vN for the amplifier if the dc input Vin is +4 V. a. OV b. None c. 2 V d. −1 V e. 1 V f. −2 V

In the following circuit assume that all transistors are operating in the saturation region. Also, assume that λ = γ = 0, VDD = 1.8 V, Vbias3 = 1.15 V, VTN = 0.4 V and VTP = −0.4 V, μnCox = 800 μA/V2, (W/L)1 = 40, μpCox = 400 μA/V2, (W/L)2 = 40, (W/L)3 = 40, and RS = 100 Ω. a) Find Vbias1 such that the bias current of M1 is I1 = 1 mA. b) Calculate the small-signal voltage gain AV1 = Vout1/Vin . c) Calculate the small-signal output impedance seen at the output node Vout1.

Design the amplifier of Fig. 1 using the 0.18−μm CMOS process in Table 1.5 with Ibias = 400 μA to provide a gain of 20 dB. Take all gate lengths L = 0.3 μm. Veff = 0.2 V. Estimate the resulting bandwidth when driving a 2−pF capacitive load. Fig. 1

A company in Urbana, IL called Prairie Technology has access to a CMOS fabrication process with the device parameters listed below. μnCox = 120 μA/V2 μpCox = 60 μA/V2 L = 0.6 μm for NMOS and PMOS transistors Vtn = 0.8 V Vtp = −1 V Wmin = 1.2 μm Design a CMOS inverter by determining the channel widths Wn and Wp of the NMOS and PMOS transistors, to meet the following performance specifications. Vth = 1.5 V for VDD = 3 V Propagation delay times tPHL < 0.2 ns and tPLH < 0.15 ns, A falling delay of 0.35 ns for an output transition from 2 V to 0.5 V, assuming a CL of 300 fF and ideal step input.`