If R = 10 ohms, and the energy stored in batteries is 1500 mAh (mili-ampere-hour), how many hours can the batteries keep the LED ON? (Write your answer in hours with no decimal points)
In the following circuit, LED must be derived with 100 mA current. Find the resistor in ohms (Write you answer without any decimal points)
The following figure shows a generic diagram for a voltage amplifier, which includes three main parts: source, amplifier, and load. Design a circuit for the amplifier part to meet the following requirements. Rin = 200 kΩ; Rout = 20 kΩ; and |Avo| = 20 V/V. Use common-source MOSFET amplifier to design the circuit. The values of resistors and DC voltage sources can be selected based on your design. Assume each capacitor may be represented by a short-circuit at the frequencies of interest. Please complete the following tasks. (a) Show a complete circuit of the designed voltage amplifier, and indicate the values of all components, including the parameters K and Vth for the MOSFET. (b) Draw the equivalent circuit for DC analysis. (c) Conduct DC analysis and find the corresponding DC quantities. (d) Draw the equivalent AC small signal circuit for the circuit. (e) Calculate the values of Rin , Rout and Avo . (f) List three methods to double the output voltage of the proposed voltage amplifier.
In the amplifier circuit, given VCC = 10 V, R1 = 160 kΩ, R2 = 40 kΩ, RC = 2 kΩ, and RL = 2 kΩ, answer the following questions. Assume the BJT has a β = 100. (a) Calculate RE to make the BJT's operating point (Q-point) current ICQ = 2 mA. (b) Assuming ro = ∞ and CE = ∞, draw the small-signal equivalent circuit of the amplifier and calculate the amplifier's input resistance (Rin), output resistance (Rout), and voltage gain (Av). (c) Assuming ro = ∞ and CE = 0, draw the small-signal equivalent circuit of the amplifier and derive the expression for the voltage gain (Av). Then, calculate the value of Av. (d) Assuming ro = 10 kΩ and CE = 0, draw the small-signal equivalent circuit of the amplifier and derive the expressions for Rin , Rout , and Av. Then, calculate their values. (e) To operate as an amplifier, in which operating region should the BJT be biased? Explain the reason with the help of the voltage transfer characteristic.
A Class A_power amplifier is shown in Figure Q3 below. Consider Rc = 20 Ω, Rb = 1 kΩ, Vcc = 20 V and β = 20. Assume Ib (rms) = 10 mA (rms) a) Calculate the efficiency of the power amplifier. [12 marks] b) Analyse the circuit and suggest whether maximum efficiency can be achieved. [4 marks] c) With the aid of appropriate diagrams show what modifications can be made to the circuit to increase the efficiency to above the efficiency limit of a Class A power amplifier. [4 marks] d) Provide details of the components you have included in the circuit and calculate the improved efficiency. [5 marks] [Total: 25 marks]
The MOSFET circuit shown below uses a MOSFET with the indicated characteristics. For each of the cases listed, solve MOSFET's device current and drain voltage, and indicate whether the device is operating in saturation or triode. [Hint: To perform this analysis, first assume the device is in saturation, and solve accordingly. Then check for consistency. If the result is inconsistent, then repeat the analysis using the triode equation.] (A) R = 100 Ω (B) R = 1 kΩ (C) R = 10 kΩ
The MOSFET circuit shown below uses a MOSFET with the indicated characteristics. For each of the cases listed, solve MOSFET's device current and drain voltage, and indicate whether the device is operating in saturation or triode. (A) R = 100 Ω (B) R = 1 kΩ (C) R = 10 kΩ
The MOSFET circuit shown below uses a MOSFET with the indicated characteristics. For each of the cases listed, solve MOSFET's device current and drain voltage, and indicate whether the device is operating in saturation or triode. (A) R = 100 Ω (B) R = 1 kΩ (C) R = 10 kΩ
The MOSFET circuit shown below uses a pair of identical MOSFETs with the indicated characteristics. For each of the cases listed, solve MOSFETs' device currents and drain voltages, and indicate whether each device is operating in saturation or triode. (A) R = 100 Ω (B) R = 1 kΩ (C) R = 10 kΩ
The MOSFET circuit shown below uses a MOSFET with the indicated characteristics. For each of the cases listed, solve MOSFET's device current and drain voltage, and indicate whether the device is operating in saturation or triode. (A) R = 100 Ω (B) R = 1 kΩ (C) R = 10 kΩ
The MOSFET circuit shown below uses a MOSFET with the indicated characteristics. For each of the cases listed, solve MOSFET's device current and drain voltage, and indicate whether the device is operating in saturation or triode. (A) vG = 4.5 V (B) vG = 4.0 V (C) vG = 3.0 V (D) Assuming the device is in deep triode (i. e. it is in the linear region), solve for the case when vG = 0 V by approximating the device as a resistor with resistance RON.
The MOSFET circuit shown below uses a MOSFET with the indicated characteristics. For each of the cases listed, solve MOSFET's device current and drain voltage, and indicate whether the device is operating in saturation or triode. [Hint: To perform this analysis, the usual procedure is to assume the device is in saturation, and solve accordingly. Then check for consistency. If the result is inconsistent, then you must repeat the analysis using the triode equation.] (A) vG = 0.25 V (B) vG = 0.74 V (C) vG = 3 V (D) Assuming the device is in deep triode (i.e. it is in the linear region), solve for the case when vG = 5 V by approximating the device as a resistor with resistance RON.
The initial parameters of an n-channel MOSFET are Cox μn = 0.15 mA/V2, L = 1.2 μm, W = 6.0 μm, and VT = 0.45 V. The device operates over a voltage range of 0 to 3 V (i. e. , 0 V < VG < 3 V ). Consider a case where the device needs to be scaled down to lower dimension. As the dimension of the MOSFET is scaled down, parameter VD, L, and μ are scaled by k and Coxμn is scaled by 1/k. Assume the scaling factor of k = 0.65, but the threshold voltage is held constant. (a) Determine the maximum drain current in the (i) original device and (ii) scaled device. (b) Determine the maximum power dissipation in the (i) original device and (ii) scaled device. Note the power dissipation can be calculated by multiplying drain voltage VD by maximum drain current ID(max) (i. e. , P(max) = ID(max)×VD)
An n-channel MOSFET is doped to Na = 3×1016 cm−3 and has an oxide thickness of tox = 20 nm. The diffused junction radius is rj = 0.30 μm. Determine the minimum channel length such that the threshold voltage shift due to short channel effects is limited to ΔVT = −0.15 V.
Consider a SRAM cache system with L1, L2, and L3 caches, perform the timing analysis using the following information. Assume L1 intrinsic access time t1 = 2 clock cycles, L1 cache miss rate is 0.1 , and L2 intrinsic access time t2 = 4 clock cycles, L2 cache miss rate is 0.05, and L3 intrinsic access time t3 = 10 clock cycles, and assume all the data could be found from L3 cache. Please calculate L1 perceived access time T1 [5 pts]
D 16.20 Consider a 6 T SRAM cell fabricated in a 0.18−μm CMOS process for which Vtn = |Vtp| = 0.5 V and VDD = 1.8 V. If during a read-1 operation it is required that VQ¯ not exceed 0.2 V, use the graph in Fig. 16.14 to determine the maximum allowable value of the ratio (W/L)5/(W/L)1. For L1 = L5 = 0.18 μm, select values for W1 and W5 that minimize the combined areas of Q1 and Q5. Assume that the minimum width allowed is 0.18 μm.
Q4 SRAM Memory Circuits [Total 20 pts ] Figure 1: A 6-transistor SRAM cell Q4.1 Consider the 6-transistor SRAM cell in fig. 1 above, complete the operation table below with voltages that need to be applied on the wordline (WL) and bitline (BL), choose voltages from VDD or 0 . [Total 14 pts, 2 pts each] Q4.2 To ensure the success of the read and write operations, there are requirements on the W/L ratios of the transistors in SRAM. Assume VDD = 1 V, Vtn = |Vtp| = 0.3 V, μn = 2 μp, choose the correct ratios of PD:PG:PU that can meet the requirements (circle one): [6 pts] (a) 1:1:1 (b) 2:1:1 (c) 1:1:2 (d) 2:2:1
Find the maximum allowable W/L for the access transistors Q5 and Q6 of the SRAM cell in the figure below, so that in a read operation, the voltage at Q and Q¯ do not change by more than |Vth|. Assume that the SRAM is fabricated in a 0.18−μm technology for which VDD = 1.8 V, Vtn = |Vtp| = 0.5 V and that (W/L)1 = (W/L)3 = 1.5. (20 points)
A Memory Cell primarily needs only TWO States to store Binary Information. An SRAM Cell is shown in the figure below. Answer following questions assuming that this cell is storing a ZERO (Low) value: What would be the status of the Node C1? ZERO (LOW) ONE (HIGH) What would be the status of the Node C2? ONE (HIIGH) ZERO (LOW) What would be the status of the Transistor T5? ON OFF What would be the status of the Transistor T6? ON OFF What would be the status of the Transistor T4? ON OFF What would be the status of the Transistor T2? OFF ON What would be the status of the Transistor T3? OFF ON What would be the status of the Transistor T1? ON OFF An SRAM Cell based memory is Volatile: TRUE FALSE Which of the following is NOT applicable to SRAM as compared to DRAM? : Needs a Refresh Circuitry Higher Cost per Bit Faster Access Bigger in Size
Consider the write operation of the SRAM cell shown below. The process parameters are given in the Appendix. The two inverters have matched pull-up and pull-down driving strength. Let (W/L)1 = (W/L)3 = m, where n denotes the W/L ratio of a minimum-size device. Initially the SRAM stores a 1(Q = 1) and a 0 is being written. Ignore the body effect and the channel length modulation effect. VDD = 2.5 V. (a) Describe the setting of WL, BL and BL¯ in this operation. (4%) (b) Find the minimum required (W/L) ratio of M5 (in terms of m ) so that node Q¯ can be pulled up to VDD/2. (7%) (c) Find the minimum required (W/L) ratio of M6 (in terms of m) so that node Q can be pulled down to VDD/2. (7%) (d) Since M5 and M6 are designed to have equal W/L ratios, which of the two values found in (a) and (b) would you choose for a conservative design? (2%)
An SRAM contains 3072 48-bit words. It is physically arranged in a fashion that requires an 8:1 column multiplexer and uses an SRAM cell that is 0.52 um×0.32 um. Assuming the periphery circuitry adds 15% to each dimension of the array, what are the X and Y dimensions of the SRAM array? X = 229.6 um; Y = 141.3 um X = 180.1 um; Y = 180.1 um X = 156.6 um; Y = 156.6 um X = 199.7 um; Y = 122.9 um X = 114.8 um; Y = 282.6 um X = 99.8 um; Y = 245.7 um
Consider a standard 6-T SRAM cell shown below, which is designed for Vdd = 1.5 V, V tn = 0.5 V, Vtp = −0.5 V. Consider that due to Random Dopant Fluctuation, transistors in a single cell may have different threshold voltages than that of what was designed for. Assume that a variation of ±50 mV in threshold voltage can happen and a "0" is stored in the cell. The threshold voltages of transistors Q2 and Q6 for the worst case read operation is a. 0.45 V, 0.45 V b. 0.45 V, 0.55 V c. 0.55 V, 0.45 V d. 0.45 V, 0.45 V
Construct a 32K×8 memory system using 2K×8 RAM chip. Suggest a schematic for this memory system to be connected to a general microprocessor as shown in Figure 1. Explain the operation of writing and reading data to and from the memory system. (14 marks) Figure 1
For the questions on this page, consider an SRAM that uses coincident selection as shown in the below figure. Remember that in our terminology, a column is a group of bitslices that are selected simultaneously. The SRAM has 8 address lines. The data width is 4 bits. What is the capacity of the SRAM (in kb)? (1 kb = 1 kilobit = 1024 bits.)
D 16.24 A 6T SRAM cell is fabricated in a 0.13−μm CMOS process for which VDD = 1.2 V, Vt = 0.4 V, and μnCox = 500 μA/V2. The inverters utilize (W/L)n = 1. Each of the bit lines has a 2-pF capacitance to ground. The sense amplifier requires a minimum of 0.2−V input for reliable and fast operation. (a) Find the upper bound on W/L for each of the access transistors so that VQ and VQ¯ do not change by more than Vt volts during the read operation. (b) Find the delay time Δt encountered in the read operation if the cell design utilizes minimum-size access transistors. (c) Find the delay time Δt if the design utilizes the maximum allowable size for the access transistors.
Problem 4.1 During a write "0" operation, we want to ensure that the state of the SRAM cell can be changed when the voltage on the bitline VC ≤ 0.5 V. Choose W/L ratios for transistors M5 and M6 to guarantee this write condition assuming that both PMOS devices must have the same W/L ratio. (Use the inverter threshold VM as the judging criterion of the state transition of memory cell) μpCox = 50 μA/V2 γ = 0.4 V12 λ = 0.0 V−1 |2ϕF| = 0.6 V For M1 and M2: W/L = 2/2 For M3 and M4: W/L = 1/2
Q5.4 State (a) has no electrons stored in floating gate, state (b) has electrons stored in the floating gate. In the following drain current vs. control gate voltage (Ids−Vcg) curve, which curve corresponds to state (a) and which curve corresponds to state (b)? [3 pts] Label clearly 1 or 0 to state (a) or state (b). Floating Gate (FG)
An 8 transistor SRAM cell design is shown below. With this design, there is a Write Word Line that is used to write the values of WBL and WBL_bar into the cell, and a separate Read Word Line that is used to read the content of the cell on the Read Bit Line (RBL). Explain the operation of this cell, and why/how it is useful. Which transistors are involved in a Write operation? Comment about their sizing limitations. Which transistors are involved in a Read operation? Comment about their sizing limitations.
The below diagrams show the pin layout of an early SRAM chipset and the timing diagram. (i) For each CS¯ input pulse at a, b, c, and d, list the mode of operation, the contents of both the Address and the Memory contents. (2 marks) (ii) What is the size of this memory chip? Show your reasoning. (4 marks) (iii) Determine the functions of the Vcc and the GND pins. (2 marks)
D 16.19 Find the maximum allowable W/L for the access transistors of the SRAM cell in Fig. 16.12 so that in the read operation, the voltages at Q and Q¯ do not change by more than |Vt|. Assume that the SRAM is fabricated in a 0.13−μm technology for which VDD = 1.2 V and Vtm = |Vtp| = 0.4 V, and (W/L)n = 1.5. Find VQ¯ and I5 that result in each of the following cases: (i) (W/L)a = 13 the maximum allowed (ii) (W/L)a = 23 the maximum allowed (iii) (W/L)a = the maximum allowed Assume μnCox = 500 μA/V2. Which one of the three designs results in the shortest read delay?
The circuit shown above is a Static RAM (SRAM) cell. a) Discuss the critical issues that must be addressed during a read operation. (10 pts) b) Discuss the critical issues that must be addressed during a write operation. (10 pts) c) Discuss what role the sense amplifier plays in the operation of the SRAM and why it requires a high voltage gain. (10 pts) d) Describe what determines the value of the capacitances CB and CB- (10 pts)
List the advantages/disadvantages of the resistive SRAM shown in Fig. 1 as compared with the conventional 6 T-SRAM cell. Explain Read and Write operation of conventional 6 T-SRAM cell. Consider (W/L)access = 3Wmin/Lmin , (W/L)pdn = 5Wmin/Lmin , (W/L)pup = 4Wmin/Lmin , VDD = 1 V, Vthn = |Vthp| = 0.4 V, Coxn = Coxp , μn = μp. Determine the read noise margin considering conventional 6 T-SRAM cell. Consider VDD = 1 V, Vthn = |Vthp | = 0.4 V, determine the sizing ratio between Access transistor and Pulldown-NMOS for reliable read operation of conventional 6 T-SRAM cell.
a) Find the maximum allowable aspect ratio for the access transistors of a SRAM cell so that in a read operation, the output voltages of the cell do not change by more than the value of the threshold voltage. The SRAM has the following characteristics: L = 0.25 μm VDD = 2.5 V VTN = 0.5 V |VTP| = 0.5 V (W/L)n = 1.5 b) Repeat part a using the following characteristics: L = 0.18 μm VDD = 1.8 V VTN = 0.4 V |VTP| = 0.4 V (W/L)n = 1.5 c) Repeat part a using the following characteristics: L = 0.13 μm VDD = 1.2 V VTN = 02 V |VTP| = 0.2 V (W/L)n = 1.5
The circuit below shows the relevant portion of an SRAM circuit during a write operation, you are given that W1 = 1.2 μm, W2 = 1 μm, and L1 = L2 = Lmin. At t = 0 seconds, the voltage vw instantaneously switches from 0 V to 3 V, which turns transistor Q2 on causing the voltage, vQ, to decrease. (note Q1 is a p-channel and Q2 is an n-channel MOSFET) a) (10 pts) Use the method of average currents to estimate the time it takes for vQ to decrease from 3 V to 1 V. b) (10 pts) Calculate the minimum value of vQ after vw is switched.
Q4. (12 points) (a) The input-output VN1−VN2 relation plot for an SRAM cell in WRITE operation mode is shown in Figure 4. Explain why we need to ensure there is only one stable point in the WRITE operation. (2 points) Figure 4 (b) How would the Vwrite0,L change if the gamma ratio (i.e. the ratio of W/L between the pull-up (PU) transistor and the passing gate (PG) transistor) of the SRAM cell is made larger? Explain why. (5 points) (c) How would Figure 3 change if the beta ratio (i.e. the ratio of W/L between the pull-down (PD) transistor and the passing gate (PG) transistor) becomes smaller? Explain why. (5 points)
SRAM (static random access memory): This problem concerns the design of a 4-resistor 2-transistor (BJT) SRAM cell (flip-flop) having a supply voltage of VCC = 5.0 V. Assume that the BJT's CE saturation voltage (VCE,sat) in the ON state is 0.2 V. Assume that the current amplification of the transistors is β = 50. (a) Draw the circuit diagram. (b) Choose one of the two stable states of the flip-flop, and indicate all circuit elements that consume power. Circle these circuit elements. (c) Write an equation for the power consumed by each of these circuit elements (circled under the previous question). Sum up all these powers (summands) to obtain the total power consumed by the circuit. Which of these summands represents the greatest power? Give the approximate power consumed by the circuit by writing an equation that has just the dominant summand. (d) Design a 4-resistor 2-transistor SRAM circuit in which the dominant power-consuming circuit element consumes a power of about 1 μW. What is the collector current? Suggest numerical values for the resistances of all four resistors. (e) What would be the power consumed by a 1 Gbit SRAM circuit using the memory cell you just designed? Do you have any comments on the result?
Figure -2 shows a block of SRAM memory that can be used to implement a memory of 8 words with 8-bits/word. An embedded SRAM, of 2048 8-bit words is built in a square configuration using multiple instances of the SRAM block in the figure. Because of the square configuration, multiplexers are used in the column decode circuitry to address each word. How many select lines are needed for this multiplexer in the column decode circuitry? Figure - 2
The circuit shown above is a Static RAM (SRAM) cell. a) Discuss the critical issues that must be addressed during a read operation. (10 pts) b) Discuss the critical issues that must be addressed during a write operation. (10 pts) c) Discuss what role the sense amplifier plays in the operation of the SRAM and why it requires a high voltage gain. (10 pts) d) Describe what determines the value of the capacitances CB and CB¯. (10 pts)
MOSFETs of an SRAM cell are to be sized in accordance with (8.4) and (8.6). MD1 is wide enough to assume Weq ≅ W5. The target values of V1 max and Vlin are 0.35−V and 0.7−V, respectively. Assuming μN/μp = 2.41 and VDD = 1.8, assign 0.50−μm to the narrowest among W1, W3 and W5, and determine the other two. Which of the following answers matches your result best? (a) W1 = 2.35 μm, W3 = 0.50 μm, W5 = 0.90 μm (b) W1 = 0.50 μm, W3 = 1.30 μm, W5 = 0.55 μm (c) W1 = 0.90 μm, W3 = 1.80 μm, W5 = 0.50 μm (d) W1 = 0.50 μm, W3 = 0.55 μm, W5 = 1.30 μm (e) W1 = 12.0 μm, W3 = 1.20 μm, W5 = 0.50 μm (f) W1 = 3.21 μm, W3 = 0.50 μm, W5 = 1.88 μm
PMOS: VT0 = −0.6 V, μpCox = 8 μA/V2, no Body Effect and Channel Length Modulation, W2/L2 = W4/L4 = 6. (a) Determine the maximum size of M5 and M6 so that the cell will not flip while reading, when the reading voltage is VDD/2. (b) Determine the minimum size of M5 and M6 so that the cell will flip while writing. Figure 4: 6-T SRAM for Problem 4
For the SRAM read operation sub-circuit below the gate length for both transistors is Lmin. The gate width of the access transistor Qa is 3 μm For t < 0 seconds, vB is pre-charged to VDD, vW = 0 V and therefore vQ = 0 V. At t = 0 seconds, vW is switched to VDD (note: since γ = 0 V1 /2, there is no body effect). a. (10) What is the gate width of the pull-down transistor, Qn if the maximum value reached by vQ for t > 0 seconds is the n-channel threshold voltage, Vt0. b) (10) What is the current, IB, at t = 0 seconds? c) (10) What is the current IB when vB has decreased 0.2 V, as indicated on the plot?
The self-biased stage shown in the figure below must provide a transconductance of 40 mS. If the bias current equals ID = 1 mA. Find the correct value of RD knowing that Vth = 0.5 V. (Round your final answer to Zero decimal places) RD = Ω
For the circuit shown in the figure below, knowing that RE = 100 Ω, β = 100 and VA = ∞. The bias current IC = 0.3 mA. Calculate the output impedance Rout (Without any approximation) Rout = Ω Write 2 digits after the decimal point.
Considering the Following circuit, let Vtn = 0.5 V and μn. Cox = 200 μA/V2 and W/L = 20.2. Neglect the channel-length modulation effect (i.e., assume λ = 0 and the transistor operates in saturation region). R1 = 50 kΩ and R2 = 110 kΩ, and V5 = 0.3 V. (Round your final answer to 2 decimal places) vG = v
Consider the circuit below, where RD = 1.6 kΩ and λ = 0, if Rin is 40 Ω, then the voltage gain Av is: (Round your final answer to zero decimal places)
For the circuit shown in the figure below, we wish to find the biasing current IC . Knowing that the current flowing through the 12 kΩ resistor is much higher than the base current (IR > > IB), VT = 26 mV and IS1 = 4×10−16 A, calculate IC. (Round your answer to 2 decimal places). IC = mA
For the circuit shown in the figure below, knowing that RC = 2.4 KΩ and VA = ∞. The input impedance Rin = 42.7 KΩ and the transconductance gm = 12 mS. find β. β =
The transistor shown in the circuit below must be biased by a collector current IC = 1 mA and VBE = 0.75 V. Knowing that β = 100, find RB without making any approximation Select one: a. RB = 14.2 kΩ b. RB = 53.8 kΩ c. None of these d. RB = 77 kΩ
Using V = 9 mV, and given the voltage across an inductor L = 10 mH as shown in Fig. P6.25, determine the waveform for the inductor current during the time t1 <= t <= t2, where t1 = 4 ms and t2 = 19 ms. Assuming the solution looks like iL(t) = Xt2 + Yt + C, what is the initial condition of the current (the constant, C)? For your answer just put the magnitude of the initial value of the constant and in milliAmps (there should only be a number in your answer). Figure P6.25