Q4) In the following MOSFET transistor, a) State the operation region of the transistor (proof whether it is in cutt-off saturation or triod region) b) Find the value of R and the dc voltage VD to obtain a current ID = 100 μA. Let the MOSFET transistor have Vt = 0.65 V, μnCox = 200 μA/V2, L = 0, 85 μm and W = 5 μm. Neglect the channel length modulation effect (assume λ = 0)
Long channel MOSFET I−V relation Consider an NMOSFET with Toxe = 10 nm, W = 10 μm, and L = 2 μm. The I−V curves are plotted in the right figure. (Use the long-channel I-V equations for your calculations.) (a) Estimate Vt from the plot. (b) Calculate the value for m (from Vdsat). (c) Estimate μns in the inversion layer. (d) Plot the I - V curve corresponding to Vgs = 3 V. You need to calculate Idsat and Vdsat. (e) Plot Id vs. Vgs for Vds = 5 V. (Here Vds > Vdsat. ) (f) Plot Id vs. Vgs for Vds = 0.01 V.
NMOS C-V curves A, B, and C are the measured C−V curves for a MOS capacitor. For this problem, assume that the poly-Si gate is degenerately doped and that the substrate is uniformly doped. (Recall that degenerately doped means the Fermi level coincides with either Ec or Ev. ) (a) Is the substrate doped with n-type or p-type? (b) Point out which of the C−V curves are measured in the low-frequency, high-frequency, or deepdepletion modes? (c) Under what experimental condition can we get the deep-depletion C−V curve? (d) What do we call V1 and V2? (e) What do we call regime 1 , regime 2 , and regime 3? (f) Is the poly-Si gate doped n+or p+? (Hint: You can tell from the polarity of Vfb. ) Sketch the energy band diagram when Vg = V2. (Assume there is no oxide charge.) (g) Sketch the energy band diagram for Vg = V1. (h) Determine Tox. (i) Determine Wdmax . (j) Determine Nsub from the values of C1 and C2. (k) Calculate Vfb. (1) Calculate Vt.
For the CMOS inverter with given voltage transfer characteristics and schematic, a) Find (VI, VO) in terms of VDD, VTn, VTp, Kn, Kp, and VM at points A, B, C, and D. For points B and C, use VM as the value of VI. b) Determine the states of the transistors in each region (I-to-V). Note that region III corresponds to the line between points B and C. You do not need to verify the states c) Derive VM in terms of VDD, VTn, VTp, Kn, and Kp. For VDD = 5 V and VTn = |VTP| = 1 V, find Kn/Kp to design a CMOS inverter with VM = 0.6 VDD = 3 V.
You have the A x B SRAM chip. Calculate the following: (a) The required address bus lines and input/output data bus lines in this SRAM chip. (b) The total number of bits stored in this SRAM chip. (c) The SRAM chip with A×B has one chip-select input (CE#), two control signals for read-memory operation (OE#) and write-memory operation (WE#). This chip operates from a 3.3 V power supply. How many pins are needed for this integrated circuit package? (d) Draw a block diagram and label all input/output terminals in this SRAM chip. (e) Using the SRAM chip with A×B, and an inverter, build the memory unit with 2 A×B.
a) (4 Points) What is the size of the memory array? (How many different words are stored in the memory array? What is the word size constructed from the four 32×4 SRAM devices?) b) (5 Points) What is the address space for each of the four 32×4 b SRAM devices? (What are the starting and ending addresses for each of the 32×4 b SRAM devices?)
P3-SRAM You are given the SRAM cell shown below. The relative sizing of the transistors is M2 = M4 = M5 = M6 = 1 and M1 = M3 = 2. a) Is the read operation stable? Briefly explain why or why not. b) Is the write operation stable? Briefly explain why or why not.
The following exercises are for a write operation associated with a SRAM cell. a) Determine the maximum value of (W/L)p in terms of (W/L)a for a 6 T SRAM that has the following properties: L = 0.25 μm VDD = 2.5 V VTN = 0.5 V|VTP| = 0.5 V μn = 3μp b) Repeat part a for a 6 T SRAM that has the following properties: L = 0.18 μm VDD = 1.8 V VTN = 0.5 V |VTP| = 0.5 V μn = 3μp c) Repeat part a for a 6T SRAM that has the following properties: L = 0.13 μm VDD = 1.2 V VTN = 0.4 V |VTP| = 0.4 V μn = 3μp
e) If a SRAM has 14 address lines and 8 data line, i. What is its organization? ii. What is its capacity? iii. How many SRAM is required to construct ONE address for 8086 ? iv. Nature of connection in (c) Byte Length or Word Capacity v. Write and alternate organization for same capacity
Find the maximum allowable W/L for the access transistors of the 6 T SRAM cell so that in the read operation, the voltages at Q and Q¯ do not change by more than |VT|. Assume that the SRAM is fabricated in a 0.13 μm technology for which VDD = 1.2 V and VTn = |VTp| = 0.4 V, and (W/L)n = 1.5. Find VQ¯ and I5 that result in each of the following cases: (a) (W/L)a = 13 the maximum allowed (5 points) (b) (W/L)a = the maximum allowed (5 points) Assume that μnCox = 500 μA/V2
A memory chip has 8 pins for data bus and 15 pins for address bus. This memory chip is Select one: a. 32K SRAM, 8 data bits b. 256K SRAM, 4 data bits c. 16K SRAM, 4 data bits d. 64K SRAM, 8 data bits
Follow the instructions below using the parameters below: *0.6 um technology. *All transistor size ( W or L ) must be divisible by 0.3 um in order to be produced by a company. *Always set the sizes of W and L assuming the smallest possible L(0.6 um ) for each transistor according to that technology. Include units. *VDD = 3 V:VTOP = 0.8 V; VTON = 0.7 V; unCox = 60 uA/V2 upCox = 20 uA/V2; gamma = 0.1 sqrt (V);2 ΦF = 0.6 V Design one bit of an SRAM memory when the capacitance of Q, CQ = 5 fF and the capacitance of the bit line is 1 pF. The access transistors in a Bit of RAM memory have a size (W/L) = 6 um/0.6 um. Determine the minimum size of the NMOS transistors in the inverters. Justify the size you are choosing for each transistor. What will happen in the cell if you decrease the inverter's NMOS W size by 0.3 um ? Calculate the minimum size of the PMOS transistors in the inverters used in the memory. What will happen in the cell if I increase the size of W by 0.3 um in the access transistor? Figure 15.12 A CMOS SRAM memory cell. Q5 and Q6 are the access transistors.
The Intel 2115 is a 1K×1 Static RAM (SRAM) chip as shown below. Note that there are ten (10) address select lines labeled A0 thru A9, one bit of data input DI, one bit of tri-state data output DO, an active low chip select CS¯, and a READ/WRITE select WE¯. Using 2115 SRAMs, design a 2K×2 SRAM system (2K words, each word consisting of 2 bits). Be sure to indicate any additional logic or hardware needed in your design. It suffices to indicate the address lines as a single bus using bus notation as shown in Fig 8.14 on p. 393 of Mano and Ciletti.
Find the maximum allowable W/L for the access transistors for the SRAM cell in below circuit so that in read operation, the voltages at Q and Q¯ do not change more than |Vt|⋅L = Lmin = 0.5 μm, VDD = 1 V, Vtn = −Vtp = 0.35 V, (W/L)n = 2
D 16.29 Design a minimum-size 6 T SRAM cell in a 0.13−μm process for which VDD = 1.2 V and Vtn = |Vt| = 0.4 V. All transistors are to have equal L = 0.13 μm. Assume that the minimum width allowed is 0.13 μm. Verify that your minimum-size cell meets the constraints in Eqs. (16.5) and (16.11).
For the SRAM cell shown below, the widths of M1 and M3 are 240 nm, the widths of M2 and M4 are 120 nm, and the widths of M5 and M6 are 120 nm. For this technology, you are given that VDD = 1 V and CD = CG = 2 fF/μm. The dimensions of the cell are 3 μm×3 μm and the cell is part of 256×256 memory array. Each bitline runs in Metal 2 with 0.12 μm width and Cpp = 7 aF/μm2, Cfr = 14 aF/μm. Bitlines are pre-charged to VDD for read, and in order to speed up the read operation, they are connected to (ideal) differential sense amplifiers, which instantly evaluate the correct output once their input differential voltage is 500 mV. a) Looking at the whole memory block, calculate the read access time assuming RN = 1.5 kΩ∗μm. (Note: Assume device capacitance on internal cell nodes is negligible. ) b) How much energy is consumed by the memory for every read/precharge operation? c) Explain qualitatively how the read and write noise margins of the cell are affected if the supply of the cross-coupled pair is lowered to VDD/2, while the bitline is still precharged to VDD. (i. e. do they get better or worse and why?)
Consider a standard 6-T SRAM cell. Use the following parameters. L = 45 nm, VDD = 1.2 V. For all the NMOS transistors, widths are 450 nm and size the pull-up PMOS transistors as three-times the widths of the pulldown NMOS transistors. |Vth| = 0.4 V⋅ μn μp = 2. a. Determine Cell ratio (ratio of the widths of pull-down NMOS and access transistor) for read. b. Determine Pull - up ratio (ratio of the widths of pull-up PMOS and access transistor) for write. c. Write the regions of operation of all the transistors for both a) and b). d. Determine VREAD. e. Determine the condition to avoid destructive read.
Consider the following 6T SRAM. Assume that a 0 is stored on the left side (i.e. VQ = 0 ) and a 1 is stored on the right side (i.e. VQ∗ = 1 ). It is desired to perform a READ operation. Initially the bit lines BL and BL* are pre-charged to VDD. After they are charged, the WL line is raised to VDD. Assume the following: All transistors have the same length, VDD = 1.2 volts, kn = 4 kp′ = 20 μA/v2, Vtn = −Vtp = 0.4 volts, ignore body effect. a. Compute the Width of transistors M1 and M3 given that the circuit can only tolerate a rise in voltage at VQ of no more than 0.1 volts during the READ operation. Assume that CBL = CBL∗ = 2 pF and that specifications calls for a 200 mvolts differential in the bit line (i. e. ΔV = 200 mvolts) in 2 nsec.
For a 64 k×8 SRAM, determine the number of i) rows = ii) columns = iii) bits = Eight output tri-state buffers
Consider an SRAM with 2 K words of 32 bits each. a) How many address bits are needed to address these words? (Reminder 1024 = 210, 4096 = 212, 16, 384 = 214, 65, 536 = 216.) b) Assuming that the central memory array has the same number of rows as it has columns, how many rows are there? c) How many words are stored in each row? d) How many of the address bits are used by the row decoder? e) How many are used by the column decoder?
For the questions on this page, consider an SRAM that uses coincident selection as shown in the below figure. Remember that in our terminology, a column is a group of bitslices that are selected simultaneously. The SRAM has 8 address lines. The data width is 16 bits. What is the capacity of the SRAM (in kb)? (1 kb = 1 kilobit = 1024 bits.)
For the SRAM read operation sub-circuit below the gate length for both transistors is Lmin . The gate width of the access transistor Qa is 3 μm For t < 0 seconds, vB is pre-charged to VDD, vW = 0 V and therefore vQ = 0 V. At t = 0 seconds, VW is switched to VDD (note: since γ = 0 V1/2, there is no body effect). a. (10) What is the gate width of the pull-down transistor, Qn if the maximum value reached by vQ for t > 0 seconds is the n-channel threshold voltage, Vt0. b. (10) Which time below is the nearest estimate of the time it takes for vQ to reach its maximum value, Vt0 (hint: use the method of average currents). circle one i. 5 ps ii. 50 ps iii. 500 ps iv. 5 ns c. (10) Which time below is the nearest estimate of the time it takes for vB to drop 200 mV below VDD (hint: most of the time occurs after vQ reaches its maximum voltage). circle one i. 30 ps ii. 300 ps iii. 3 ns iv. 30 ns technology parameters VDD = 3 Vkn′ = 2 mA/V2 kp, = 0.5 mA/V2 γ = 0.0 V1 /2 2ф. = 0.6 Vλ = 0 V−1 Lmin = 0.5 μmWmin = 0.5 μm|Vto| = 1 V for both n and p channels ( 30 points)
Find the maximum allowable W/L for the access transistors of the SRAM cell shown below so that in a read operation, the voltages at Q and Q¯ do not change by more than |Vt|. Assume that the SRAM is fabricated in a 0.18 μm technology for which VDD = 1.8 V, Vtn = |Vtp| = 0.5 V and that (W/L)n = 1.5.
Problem 7: Consider the CMOS SRAM cell and data lines as shown, biased at VDD = 2.5 V. Assume transistor parameters kn′ = 80 μA/V2, V tn = 0.4 V, kp′ = 35 μA/V2, Vtp = −0.4 V, W/L = 2(MN1 and MN2), W/L = 4(MP1 and MP2), and W/L = 1 (all other transistors). Assume initially that Q = 0 and Q¯ = 1. Assume the row is selected with X = 2.5 V and assume the data lines, through a write cycle, are D¯ = 0 and D = 2.5 V. Determine the values of Q¯ and Q just after the row select has been applied.
Consider the 6 T SRAM cell. Assume a '1' is initially being held at Q and we are writing a '0' from BL to the cell. Let WM1 = WM2 = WM3 = WM4 = 0.5 μm. Find a constraint on the width of M6 such that '0' can be written into the cell. Ignore impact of BL¯ and M5 (that is, do not consider the help from M5 in causing a voltage change at Q¯). Assume the bit-line is driven by strong NMOS driver having a Wn = 5 μm. Ignore body-effect.
For the 6 T SRAM cell shown below, select all statements below that are true. When performing a read operation, the Bit line (B) and Bit_bar line (Bbar) are pre-charged to VDD Volts. When reading a logic 1 from Q (and logic 0 from Q bar), the right half of the circuit comprising Q3 and Q6 is conducting. When reading a logic 0 from Q (and logic 1 from Q bar), the right half of the circuit comprising Q3 and Q6 is conducting. During the write operation, both Q and Qbar are simultaneously set to B and Bbar using the two conducting access transistors, Q5 and Q6.
Problem 1.6-Transistor SRAM Cell: For this problem assume VDD = 1.8 V. i. Plot the voltage rise inside the cell (ΔV) as a function of cell ratio (CR). CR is defined as CR = (W/L)1/(W/L)5 ii. Plot Cell voltage (VQ) as a function of pull-up ratio (PR) of the cell. PR is defined as PR = (W/L)4/(W/L)6 iii. Using these figures, size the transistors in the SRAM. iv. Simulate your design using Cadence and verify its proper operation. (i. e. you should be able to write 0 or 1 into the cell as well as read 0 or 1 from it whout changing the data that was stored. v. Suppose that the Bit-line is precharged to VDD and that the sense amplifier can detect a voltage swing of 200 mV. Determine how long the read operation would take, given that the Bit-line capacitance is 1 pF and the delay of the sense amplifier itself may be ignored.
The chip shown is most likely a (SRAM, DRAM, or EPROM) chip. It has addresses, and its cell size is bit(s), making it a K x -b memory chip. This chip can store KB.
Question 4. [6] You are required to design the smallest SRAM cell satisfying the read stability and writability requirements in a 0.13 μm process. The process parameters are given below. Assume Lmin = 2 λ, and Wmin = 4 λ. Kn′ = 3 Kp′ = 300 μANVtn = |Vtp | = 0.4 VVDD = 1.2 VCdμ = Cgμ = 1 fF/μm a) [4] What are the widths of M1, M3, and M5 if only integer transistor W/L ratios are allowed? W1 = W3 = W5 =
Consider the SRAM cell of Figure 8.8 with a stored 0 on the left side and a stored 1 on the right side. Design the transistors of the SRAM such that node q does not exceed VTN during a read operation and node q¯ drops below VS during a write operation. The desired cell current during a read operation is 300 μA. Use 0.18 μm technology parameters. Figure 8.8 6 ST SRAM cell.
Consider a resistive load SRAM cell schematic shown below, also known as 4 transistor SRAM cell. (a) Assume that node Q is in state 1 . In order to write a 0 to node Q, bit line, BL, is lowered to 0 V. Determine the minimal size of transistor M1 so that the cell just flips when this cell is selected. Assume that the switching threshold VM of the resistive load inverter equals 0.6 V. Also, assume that VDD = 2.5 V, RL = 100 KΩ VTn = 0.4 V, and Kn = 100 μA/V2. Ignore body effect. (b) Now assume that node Q is in state 0 . In order to read the cell, both bit lines, BL and BL, are pre-charged to VDD. Determine the minimum size of transistor M2 so that the cell does not flip during a read operation. Assume that (W/L)1 = 1.2, which satisfies the constraint in part (a).
D 16.20 Consider a 6 T SRAM cell fabricated in a 0.18−μm CMOS process for which Vtn = |Vtp| = 0.5 V and VDD = 1.8 V. If during a read-1 operation it is required that VQ¯ not exceed 0.2 V, use the graph in Fig. 16.14 to determine the maximum allowable value of the ratio (W/L)5/(W/L)1. For L1 = L5 = 0.18 μm, select values for W1 and W5 that minimize the combined areas of Q1 and Q5. Assume that the minimum width allowed is 0.18 μm. Figure 16.14 The normalized value of Vϱ¯ versus the ratio (W/L)5/(W/L)1, for the circuit in Fig. 16.13. This graph can be used to determine the maximum value permitted for (W/L)5/(W/L)1 so that VQ¯ is kept below a desired level.
You are required to design a SRAM cell with the minimum area in 65 nm CMOS process. Process parameters are given next to the figure below. VDD = 1 VVtn = Vtp = 0.3 VCox = 17 fF/μm2 μn = 3 μp = 0.06 m2 /VsLmin = 65 nmWmin = 130 nmλ = 30 nm a) [2] Calculate the smallest possible sizes of M3, M5 to satisfy the writability condition. (Hint: please assume that the read speed is not important). W3 = W5 =
A CMOS SRAM cell shown in the previous slide is fabricated in a 0.18−μm process for which Vtn = |Vtp| = 0.5 V and VDD = I. 8 V. The inverters have (W/L)n = 0.27 μm/0.18 μm. Assume that a cell containing a I must be read. (a) Determine the maximum value of (W/L)5 to ensure that the cell will not change state. (b) Determine the read delay Δt in two cases: (i) (W/L)5 = 2.5 and (i) (W/L)5 = 1.5. Let μnCox = 300 μA/V2, CB, = 2 pF, and the minimum change in voltage required by the sense amplifier be ΔV = 0.2 V.
D 15.21 For the 6 T SRAM of Fig. 15.12, fabricated in a 0.18−μm CMOS process for which VDD = 1.8 V, Vt0 = 0.5 V, 2ϕf = 0.8 V, and γ = 0.3 V1/2, find the maximum ratio (W/L)5 /(W/L)1 for which VQ ≤ Vt0 during a read-1 operation (Fig. 15.13). Take into account the body effect in Q5. Compare to the value obtained without accounting for the body effect. figure 15.12 A CMOS SRAM memory cell.
16.16 Repeat Exercise 16.4 for an SRAM fabricated in a 0.25−μm CMOS process for which VDD = 2.5 V and Vt = 0.5 V. EXERCISE 16.4 Find the maximum allowable W/L for the access transistors of the SRAM cell in Fig. 16.12 so that in a read operation, the voltages at Q and Q¯ do not change by more than |Vt|. Assume that the SRAM is fabricated in a 0.18−μm technology for which VDD = 1.8 V, Vtx = |Vφ| = 0.5 V and that (W/L)n = 1.5. Ans. (W/L)a ≤ 2.5 Figure 16.12 A CMOS SRAM memory cell.
For the the SRAM cell in the figure below : a. Find the Maximum allowable W/L for the access transistor of the SRAM cell in the figure below so that in a read operation, the voltage at Q and Q¯ do not change by more than |Vt|. Assume that the SRAM is fabricated in a 0.18 μm technology for which VDD = 1.8 V, Vtn = |Vtp| = 0.5 V and (W/L)n = 1.5 b. Determine the read delay Δt when (W/L)5 = 1.5. Let μnCox = 300 μA/V2. And CB = 2 pF and the sense Amplifier requires a ΔV of minimum magnitude of 0.2 V. [Hint: determine Is and recall that VQ¯ = Vt.]
A static random access memory (SRAM) unit cell for storing one bit of information can be constructed using several CMOS transistors as shown below: (a). In the above circuit diagram of an SRAM cell, the circuit in the dashed-line box consists of two identical logic gates. What is the logic gate in such an SRAM cell? (1 mark) (b). Sketch a schematic diagram of the circuit in the dashed-line box at the logic gate level. You must use the standard logic gate symbols and show the signal interconnections clearly with proper labels. (6 marks) (c). Sketch a schematic diagram of the circuit in the dashed-line box at the transistor schematic level. You must use the standard circuit symbols of CMOS transistors and show the electrical connections (to M5&M6 as well as the power supply and ground) clearly with proper labels. (10 marks) (d). Assume a six-transistor SRAM cell. If each MOS transistor on average occupies a chip area of 16 λ×10 λ, determine the approximate memory size of a chip of 1 cm×1 cm implemented in a 40 nm CMOS technology? Express your answer in terms of megabyte (MB) or gigabyte (GB). (8 marks)
Consider a standard 6-T SRAM cell shown below, which is designed for Vdd = 1.5 V, Vtn = 0.5 V, Vtp = −0.5 V. Consider that due to Random Dopant Fluctuation, transistors in a single cell may have different threshold voltages than that of what was designed for. Assume that a variation of ±50 mV in threshold voltage can happen and a "0" is stored in the cell. The threshold voltages of transistors Q2 and Q6 for the worst case read operation is a. 0.45 V, 0.45 V b. 0.45 V, 0.55 V c. 0.55 V, 0.45 V d. 0.45 V, 0.45 V
Based on the 6-transistor SRAM cell shown above, select all statements that are TRUE. During the write operation, both Q and Qbar are simultaneously set to B and Bbar using the two conducting access transistors, Q5 and Q6. During the read operation, both Q and Qbar are simultaneously set to B and Bbar using the two conducting access transistors, Q5 and Q6. During the write operation, both Q and Qbar are simultaneously set to logic 1 using the two conducting access transistors, Q1 and Q3. During the read operation, both Q and Qbar are simultaneously set to logic 1 using the two conducting access transistors, Q1 and Q3.