Consider the following structure of dynamic MOS logic circuits. Assume that the minimum size of NMOS is 3 units (n = 3) and PMOS is 4 units (p = 4) with channel length of 0.1 μm (L = 0.1 μm). Determine the minimal channel width (in μm ) of each of the transistor below, so that the logic is operational. (20%) (c)
An n-channel enhancement-mode MOSFET has the following parameters: conductance parameter, Kn = 3 mA/V2 and threshold voltage, VT = 1.5 V. The MOSEET is operating with VGS = 2 V. a) Determine the value of VDS (sat) b) If the MOSFET is operated in the saturation region with VDS = 14 V, determine the value of the drain current, ID c) If the MOSFET is operated in the saturation region with VDS = 14 V, determine the value of the transconductance in saturation d) If the MOSFET is operated in the nonsaturation region with VDS = 0.6 V, determine the value of the drain current, ID. e) If the MOSFET is operated in the nonsaturation region with VDS = 0.6 V, determine the value of transconductance in nonsaturation
Find the state of NMOS and PMOS in region 1 and 2. Show your reasoning with numbers. Assume Vt to be 0.5 V for NMOS and - 0.5 V for PMOS Voltage-Transfer Characteristics (VTC)
In the circuit below, VDD = 3 V, R1 = 50 kΩ, R2 = 100 kΩ, R3 = R4 = 5 kΩ, Rs = 1 kΩ and RL = 30 kΩ, C1, C2 and C3 have large values. The transistor operates at the DC point of ID = 0.2 mA, VDS = 1 V and VGS − VTN = 0.5 V. The transistor has λ = 0.1 V−1 and a negligible body effect. (a) Identify the circuit as a common-source, common-drain, or common-gate amplifier. (b) Calculate the small-signal parameters gm and rds of the transistor. (c) Draw an AC small-signal equivalent of the circuit, with the transistor represented by its small-signal model. (d) Calculate the AC small-signal voltage gain vo/vs. (e) Calculate the AC small-signal input and output resistances Rin and Rout.
Assume there is a MOS capacitor. The metal used in the capacitor is TaN, the oxide material is SiO2, and the substrate is p-type Si. At 300 K, the doping concentration of the p-type substrate NA = 1.5×1017 cm−3. The fixed charge in the gate oxide QS is 1011 cm−2, the work function of TaN is 4.02 eV, and the electron affinity of Si and SiO2 are 4.01 eV and 9 eV, respectively. The MOS capacitor was measured by a semiconductor analyser. It was found the maximum capacitance is 5×10−8 F/cm2. Provided that, at 300 K, ni = 1.5×1010 cm−3, ε0/e = 5.52×105 F cm−1 C−1, please calculate: i. The gate oxide thickness tox and capacitance Cox. (10 pts) ii. The flatband voltage VFB. (5 pts) iii. The maximum depletion width Xd and the depletion charge density Qd. (20 pts) iv. The threshold voltage VT. (5 pts) v. If the gate metal TaN is replaced by a heavily n-type doped (n++)Si, what is the impact on the capacitance of the MOS device? Please discuss it qualitatively. (10 pts)
(a) An engineer was measuring the high-frequency C−V characteristic of a MOS capacitor with a ptype substrate and 100Å thick gate oxide. In order to measure the maximum depletion region width in the inversion mode (threshold voltage = 2 V), he swept the gate voltage, VG, from -4 V to +4 V. At VG = +4 V, he recorded the capacitance value (C1) while keeping the voltage constant. However, after reading the C1 value, he found that the C1 value was increasing with time and finally settled to another value C2. In this case, is his estimated maximum depletion width based on the C1 value reliable? Explain your answer. Why does this situation happen? What parameter must be adjusted in the measurement to avoid this situation? (10 pts) (b) Figure Q1.1 is the capacitance-voltage characteristic of a MOS structure on p-type substrate, measured at 1 MHz. In this measurement, a MOS transistor is used and the source, the drain, and the substrate terminals are grounded. Is this result reasonable? Explain. (15 pts) Fig. Q1.1
(a) For the amplifier circuit shown in panel (a), M2 is implemented as a diode-connected NMOS. (W/L)1 = 50 μm/0.5 μm, (W/L)2 = 10 μm/0.5 μm, both M1 and M2 are in saturation with IDS1 = IDS2 = 0.5 mA. Calculate the small-signal voltage gain. (b) Everything remains the same except that M2 is now implemented as a diode-connected PMOS. Calculate the small-signal voltage gain.
Given R1 = 900 kΩ, R2 = 450 kΩ, RF = 5 kΩ, RS = 18 kΩ, RD = 33 kΩ, R3 = 47 kΩ, VDD = 10 V, VTP = −1 V, Kp = 75 μA/V2, λ = 0 for DC and λ = 0.01 V−1 for AC, for the parameters of the amplifier below: a) Draw the DC equivalent circuit and calculate the Q-point. b) Draw the AC equivalent circuit with the small signal model for the transistor. c) Calculate the voltage gain, Av. Neglect r0. d) Draw the circuit to find the amplifier input resistance ( Rin). e) Calculate Rin. f) Draw the circuit to find the amplifier output resistance (Rout). Do not neglect r0. g) Calculate Rout.
For the simple inverter shown below, the unrealistic PMOS and NMOS transistors made-up for this problem have on-resistances: RONn = R, RONp = 3R, and VTHn = VTH, ITHpI = 2VTH. Sketch the voltage transfer characteristic for this gate. Assume the simple ON/OFF switch model for the transistors, and clearly annotate all the breakpoints in terms of VDD and VTH. Calculate the noise margins. Answer in terms of coefficients, VDD and VTH. What is VOH? What is VoL? What is VIH? What is VIL? What is NMH ? What is NML? What is Vout when Vin reaches VTH?
The MOS transistors have the following characteristics: nMOS:Vtn = 0.7 V, Kn′ = 200 μA/V2. Assume VDD = 5 V. The required current ID1 = 100 μA the output voltage ( Vout) should be allowed to swing to a low of 0.2 V and the DC value of VOUT = 2.5 volts. Also design for current IREF = 50 μA. (a) Find the (W/L) ratio of all transistors and (ii) the resistor R. For this part you may assume there is no channel length modulation. ( 25 points). (b) Show a clean and labeled small signal equivalent circuit with the values shown. Assume all transistors have |λ| = 0.02 V1 (10 points) (c) Find both an expression and the numerical value for the small signal gain vo/vin, and Rout . 15 points)
For the common-gate amplifier below is operating with gm = 0.6 mS, RI = 50 Ω, R4 = 3 kΩ, and RL = 82 kΩ : a) Draw the AC equivalent circuit with the small signal model for the transistor. b) Calculate the voltage gain, Av. Neglect r0. c) Draw the circuit to find the amplifier input resistance ( Rin). d) Calculate Rin. e) Draw the circuit to find the amplifier output resistance ( Rout ). (Hint: since Q = point is unknown assume λ = 0). f) Calculate Rout.
Calculate the small signal voltage gain of the CS amplifier if IBIAS = 1 mA, RD = 1 kΩ, RL = 2 kΩ and VDD = 2.5 V NMOS has VT = 0.5 V, μnCox = 100 μA/V2, W/L = 10 μm/0.18 μm and λ = 0 Determine VBIAS such that the NMOS transistor operates in saturation if the minimum required voltage drop of the current source is 0.5 V Solution: Av = −2.2 V/V and 1.6 V ≤ VBIAS ≤ 2 V
For a PMOS transistor kp = 80 μA V2, and Vtp = −1.5 V. The gate is tied to ground and Vs = 5 V. Determine the mode of operation (triode or saturation) and calculate the drain current ID for VD = 4 Volts and VD = 1.5 Volts (For VD = 4 V, ID = 240 μA; for VD = 1.5 V, ID = 490 μA ) Note that when VD = 1.5 V, the transistor is right on the line between the triode and saturation regions, so either equation for ID will give you the same value of ID.)
Consider an NMOS device with the I-V characteristics shown below. (a) Find the common-source small-signal model around the operating point at VDS = 6 V and VGS = 2.5 V. Note that you will have to add a resistor between the drain and the source in your model, often denoted as ro. (b) If this transistor is then used in the circuit below: What is the small-signal voltage gain, Av = vo/vin?
5 Current mirror loaded differential pair An nFET differetial pair is loaded with a pFET current mirror and an ideal current source provides a bias current IB of 100 μA (i. e. this is a current mirror loaded differential amplifier, see illustration). Compute its differential small signal gain A = vo vi+ − vi− if kn = kn′WL = 500 μA and kp = kp′WL = 300 μA and the Early voltage VA = 1 λ = 20 V for both type of transistors is. Give all answers with at least three significant digits accuracy! Note the specific units that the answers should be given in (i. e. do not overlook any 'micro-', 'milli-', 'mega-' or similar prefixes!
For the transistors in the homework, assume VDD = 1.8 V, μnCox = 100 μAV−1, μpCox = 50 μAV−1, Vthn = 0.4 V, Vthp = −0.5 V, λn = λp = 0.05 V−1 In the inverter of Fig. 1, the output low level must remain below 150 mV. If (W/L)2 = 3 μm/0.18 μm, determine the minimum required width of M1 in case L1 = 180 nm. Find the static power consumption of the inverter in case where VOL = 150 mV.
Consider the circuit to the right. Vdd = 10 V, R2 = 20 kΩ, R4 = 2 kΩ, kn = 10 mA/V2 and Vtn = 1.5 V. Find values for R1 and R2 such that ID = 300 μA ± 1%. What is VDS in this case?
For the following two stage CS-CS E-MOSFET amplifier circuit, derive i. (1 pt) The voltage gain, AV = VL VS (No Partial Credit) ii. (1 pt) The current gain, Ai = iL is (No Partial Credit)
You are given a CMOS logic circuit for which the pull-up network with PMOS transistors has been provided below. (a) Complete the pull-down network with NMOS transistors. (b) For the NMOS transistors in the pull-down network, we'll label the one that uses A, B, C, and D as input as M5, M6, M7, M8, respectively. If inputs A and B are at logic 0 and C and D are at logic 1, determine which of the transistors (M1~M8) are ON and which are OFF. (c) Determine the logic function that is implemented by this CMOS logic circuit.
You are given that VTH = 1 V, VGS = 3 V, VDD = 18 V, and RD = 225 Ω. Use the ID−VDS characteristics to find the transistor parameter k and the value of ID that results when operating at VDS = 9 V. Note: You may want to use equations for improved accuracy. ID = number (rtol = 0.01, atol = 1 e−05) mA
The MOSFET in the common-source amplifier in the figure below is operating at gm = 5 mA/V and has Cgs = 1 pF and Cgd = 0.2 pF. Channel-length modulation is negligibly small. (a) Find the midband voltage gain in dB. [5 marks] (b) Find the upper 3-dB frequency fH. [7 marks] (c) Find the value of CG that places the pole it introduces at 1 Hz. [4 marks] (d) Find the value of Cs that places the pole it introduces at 100 Hz. [4 marks] (e) Find the value of CD that places the pole it introduces at 10 Hz. [4 marks] (f) Sketch and carefully label the Bode plot for the gain magnitude in the STC form. Specify the lower 3-dB frequency fL. [8 marks]
The ID vs. VDS curve of a certain nMOS transistor (with VGS − VTH = 2 V) is the piecewise-linear connection of ID = kVDS(VGS − VTH) and ID = k(VGS − VTH)2 plotted above as each of two dotted lines. Note that these dotted lines extend these equations into regions in which they are not valid. The transistor is loaded with RD = 100 Ω and VDD−9 V. This load line has been plotted using a solid black line. Recognize that ID = min{kVDS(VGS − VTH), k(VGS − VTH)2}. In words, the load line will intersect both dashed lines, but the intersection point with the lowest drain current, ID. is the correct operating point. What is that operating point, (VDS, ID) ? Comment: Alternately, the region in which the operating point of MOSFET exercise resides (active vs. Ohmic) can often be first determined by locating the graphical intercept points. You can then find an accurate solution by applying the region-specific equation for the piecewise-linear IV characteristic of the MOSFET. VDS = number (2 significant figures) V ID = number ( 2 significant figures) mA
For the gate shown below, assume the equivalent resistance of NMOS and PMOS transistors are Rn = 10 kΩ and Rp = 20 kΩ, respectively, and an equal junction capacitance of 0.1 fF for W L = 1. Ignore channel length modulation, and any other capacitances, but do not ignore the internal node junction capacitances. a. (2) What function is implemented by this circuit? b. (2) Size the transistors for equal worst case pull-up and pull-down resistances. c. (6) Devise a stick diagram representing the circuit layout. d. (8) Find the input patterns that give the worst-case low-to-high propagation delay (tpLH), and find this delay. e. (8) Redo part d for the worst-case high-to-low propagation delay (tpHL) f. (6) Calculate the logical effort for each of the inputs, and the gate parasitic delay. g. (6) Estimate the activity factor, αY0→1, for the output F, if P(A = 1) = P(B = 1) = P(C = 1) = 1/2. What is the energy dissipated for 0→1 transition? Assume VDD = 1 V, and for this part only, a total capacitance of 1 fF at output only.
The figure below shows a voltage divider bias circuit for an n-channel enhancement mode MOSFET, which has a threshold voltage VT = 0.6 V and K = 2.1 mA/V2. If the source current IS and the drain current ID are both equal to 6 mA, give a value for the gate current IG. Give your answer to the nearest mA.
Consider the given pull-down network for a complex CMOS gate shown below. (a) Draw the dual pull up network. (b) Write the Boolean function representing the gate. (c) Size all transistors so that it has the same delay of a standard inverter (i. e. 1X NMOS and 2X PMOS).
(3) (A) Calculate the drain current in a PMOS transistor for VGS = 0 V, −1 V, −2 V and −3 V, with VDS = −0.1 V. You are given that W = 10 μm, L = 0.2 μm, VTP0 = −1.3 V and Kp′ = 80 μA/V2. Take λ = 0 and γ = 0. Is this an enhancement or depletion mode MOSFET? (B) Calculate the drain current in a PMOS transistor for VGS = 0 V, 1 V, 2 V and 3 V, with VDS = −0.1 V. You are given that W = 10 μm, L = 0.2 μm, VTP = 1.3 V and Kp′ = 80 μA/V2. Take λ = 0 and γ = 0. Is this an enhancement or depletion mode MOSFET?
FETS can be used to either pull an output high or to pull it low, but NFETs are generally better in digital applications for pulling outputs low and PFETs for pulling outputs high. Consider an NFET with characteristics: kn′ = 115 μA/V2, VT0 = 0.43 V, λ = 0.06 V−1, VDSAT = 0.6 V, W L = 2, and a supply voltage of Vdd = 2.0 V.
5.1 Design a resistive-load inverter with R = 1 kΩ, such that VOL = 0.6 V. The enhancement-type nMOS driver transistor has the following parameters: VDD = 5.0 V VT0 = 1.0 V γ = 0.2 V1/2 λ = 0 μnCox = 22.0 μA/V2 (a) Determine the required aspect ratio, W/L. (b) Determine VIL and VIH. (c) Determine noise margins NML and NMH.
Consider this inverter circuit with the following parameters: VTn = 1 V, Kn′ = 1 mA/V2, (W/L)n = 1, λn = 0 V−1, VTp = −1 V, Kp′ = 1 mA/V2, (W/L)p = 1, λp = 0 V−1, VDD = 5 V a) If Vin = 0 V, what region will the PMOS and NMOS devices operate in? Find Vout. b) If Vin = 5 V, what region will the PMOS and NMOS devices operate in? Find Vout. c) If Vin = 3.5 V, what region will the PMOS and NMOS devices operate in? Find Vout .
Consider the CMOS inverter circuit with a capacitor connected at its output as shown below. Here Kn′ = 2 mA/V2 and VTn = 1.5 V, Kp′ = 1 mA/V2 and VTp = −0.5 V, all MOSFETs have L = 1 μm, and remember that K = K′(W/L). For a MOSFET in triode, use the S-R model with RON = 1 /K(|VGS| − |VT| ) (works for both nFET and pFET). a) Design Wp and Wn such that the overall circuit threshold, VTH, occurs at VDD/2 as shown in the graph. Here you can assume that at the threshold point VIN = VOUT = VTH. Use the smallest integer values you can for Wp and Wn, assuming the minimum width allowed is 1 μm. b) When VIN = VDD, draw the equivalent circuit. What is the time constant? c) When VIN = 0, draw the equivalent circuit. What is the time constant? d) Based on your answers from (b) and (c), which transition do you expect to be fastest: when vOUT transitions from VDD to 0 V, or when vOUT transitions from 0 V to VDD ? Why?
Unless otherwise specified, assume that circuit and device parameters are as follows: Vdd = 5 V; VTn = VTP = 1 V; μnCox = 50 μA/V2; μpCox = 25 μA/V2; λn = λp = 0.01 V−1; An NMOS current source with ID = 0.5 mA must operate with drain-source voltages as low as 0.4 V. If the minimum required output impedance is 20 kΩ, determine the width and length of the device. Figure 1 Figure 2
For a 2 input NOR gate, what is the worst case falling delay with a fan-out of 1? (worst case is when only one of the nMOS transistors is ON) 6RC 15RC 11RC 9RC
The circuit below is a MOS differential amplifier. Transistors M1 and M2 are identical and have VTN = 0.5 V, Kn = 32 mA/V2 and λ = 0.1 V−1. The VIB of the current source cannot be lower than 0.2 V and the current source is considered ideal otherwise. a) Let v1 = v2 = VCM. What are the minimum and maximum values of the common-mode voltage VCM so that M1 and M2 operate in the saturation region? (6%) b) Find the gm and ro of M1 and M2 under the conditions of part a). (4%) c) Let v1 = VCM + vid 2 and v2 = VCM − vid 2, where vid is small and VCM satisfies the conditions in part a). Draw small-signal AC half circuits of the amplifier. (4%) d) Based on part c), find the differential voltage gain (vd2 − vd1)/vid of the amplifier. (6%)
An nFET is to be operated in the saturation region/active region at a current of 20 μA. It's kn′W L = 70 μAV2 and its threshold voltage Vtn = 650 mV. (You may assume parameter λ = 0). What is its required gate to source voltage vGS and minimum drain to source voltage vDS, min = Vsat? Give all answers with at least three significant digits accuracy! Note the specific units that the answers should be given in (i. e. do not overlook any 'micro-', 'milli-', 'mega-' or similar prefixes)! vGS = V Vsat = V
For the following logic functions: a. Design the PUN and PDN. b. Identify the input combinations that the PUN will be conducting and for each combination determine the PUN resistance, rPUN , in terms of rSDP of a single PMOS component. c. Identify the input combinations that the PDN will be conducting and for each combination determine the PDN resistance, rPDN , in terms of rDSN of a single NMOS component. d. Using kn = kp = 5 mA/V2, Vtn = |Vtp | = 1 V, and VDD = 3 V, determine rDSN and rsDP . Y = A¯⋅B⋅C¯ + D¯⋅B¯Y = A¯⋅B¯⋅C¯ + D + B¯
Fig. 3 shows a cascaded two-stage amplifier. Only consider thermal noise. Assume each PMOS and each NMOS have finite output resistance, ro. Given gmb = 0. Please derive the NF (You can keep the form of R1∥R2 if it is existing in your derivation, and no need to expand it.): Fig. 3: Cascaded stages.
The NMOS transistor in the circuit below has μnCox = 0.4 mA/V2, W/L = 25, and Vt = 0.4 V. (a) Find the value of VGS that results in saturation mode operation with a dc current of ID = 0.1 mA. Neglect the Early effect. (b) Find the value of RD that results in a dc drain voltage of 0.5 V. (c) Find gm and ro at the dc operating point specified above. Assume VA = 5 V. (d) Find the open-circuit voltage gain Avo. (e) If a sinusoidal signal with peak amplitude v^i is superimposed on the dc voltage VGS, find the maximum allowable value of v^i for which the transistor operates in saturation.
CMOS Inverter. Consider the CMOS inverter circuit shown below. Neglect channel length modulation effects (λ = 0) and assume you place a load resister RL at the output. Intuitively plot the transfer function (Vout vs. Vin) you expect to see while varying Vin from 0 to VDD.
Consider the C2MOS latch shown below. Assume VDD = 1 V, gate capacitance of 3 fF for both NMOS and PMOS (3 fF is all of gate contribution for a given device), junction capacitance of 2 fF for both NMOS and PMOS (2 fF is all of source/drain contribution for a given device), and Rn = Rp = 2 kΩ. Do not ignore the internal node capacitances, but assume source/drain sharing wherever appropriate. There is no external load on output. a. (7) Calculate the worst case D to Q¯ delay of this latch. Assume that the CK input has stabilized well before the clock transition. b. (7) Calculate the worst case CK to Q¯ delay of this latch. Assume that the D input has stabilized well before the clock transition. c. (8) What are the latch setup and hold times?
A large-signal AC equivalent circuit of a common-drain n-channel enhancement MOSFET amplifier is shown. The output voltage is taken across the load resistor, RL. The load resistance is 33.3 kΩ, and the source resistance, Rin, is 180 kΩ. The MOSFET in the circuit is biased into saturation at a gate source voltage of 4.5 V and a threshold voltage of 0.8 V. The conductivity factor of the MOSFET is 100 μA/V2. For a small-signal equivalent circuit, assume the output resistance is effectively infinite. Using small-signal analysis, what is most nearly the voltage gain, vout/vin, of this amplifier?
In the circuit below, the operational amplifier is ideal with the output voltage limitations V+ = 12 V and V− = −12 V. D is an ideal diode. a) Derive the symbolic expression for Vo in terms of VI. You should clearly show every step in your answer. b) For Ri = 12 kΩ, RF = 3 kΩ, RL = 5 kΩ and with the Vi = 8⋅sin(ωt) input voltage signal, calculate V0 and draw V0 voltage waveform with respect to Vi specifying the important values on the axes on the plot(s). Every numerical value on the plot(s) should be explained in detail on your answer sheet. c) What is the function of this circuit? Considering its function, what is the most important drawback (if any) of this circuit? Explain your answer.
The voltage regulator in the circuit is to power a car radio at a load voltage of VL = 9 V from an automobile battery whose voltage may vary between 11 and 13.6 V. The current in the radio will vary between 0 (off) to 100 mA (full volume). Use the ideal equivalent circuit for the zener. a. Find Ri b. IZK and IZM if IZK = 0.1 IZM. c. Simulate the circuit in LTspice using the diode model specifying the appropriate breakdown voltage.
In an automobile car, there is an adaptor that converts voltage from 12 volts to 5 volts for smart phone charging system. The adaptor consists of a zener diode with nominal voltage of 5.1 volts. The specification is given as: IZT = 20 mA, ZZT = 17 Ω, IZK = 0.25 mA, dan IZM = 40 mA. a. [5 points] Calculate maximum voltage that can be produced by the zener. b. [5 points] Calculate minimum R that prevents current on the zener excessive. c. [5 points] Calculate voltage on the zener when the power on load is maximum. d. [5 points] Calculate allowed maximum load power so that the voltage on the zener is not drop.
p-n Junctions. A silicon diode has an abrupt alloy doping profile at the junction with NA = 1021 m−3 and ND = 1020 m−3. The Fermi level is 0.40 eV above the valance band on the p side and 0.50 eV below the CB on the n side. Given that the permittivity of Si = 12ε0, and the junction area is exactly 1 mm2, calculate: (i) V0 (the contact P. D. across the junction at zero bias), and (ii) for a reverse bias of 0.50 V, calculate (1) the barrier height VB, (2) the maximum field in the depletion layer, and (3) the depletion layer capacitance.