(a) An LTI system is described by the following differential equation: (10 points) d2y(t) dt2 + 2dy(t)dt − 8y(t) = 3x(t) Use Laplace Transform to find the Transfer Function, H(s). (b) Assume the transfer function H(z) of the system is given by the following transfer function: (10 points) H(z) = 3 s2+2s−8 Determine the Impulse Response, h(t), which is the inverse Laplace Transform of the transfer function H(z). You might use the attached Laplace Transform Table.
Consider a logic inverter having a voltage transfer characteristic consisting of 3 straight line segments, two horizontal ones at VOut = VOH = 5 V, at VOut = VOL = 0.5 V, and the third joining the points Vin = VIL, max = 2 V and Vin = VIH, min = 3.5 V. Find the NML and NMH. NML = 1.5 V and NMH = 2 V NML = 2.5 V and NMH = 2.5 V NML = 1.5 V and NMH = 1.5 V NML = 2 V and NMH = 1.5 V
When a physical contact between a p-region & n-region is established which of the following is most likely to take place? Electrons from N-region diffuse to P-region. Holes from P-region diffuse to N -region. Both of the above mentioned statements are true. Nothing will happen.
Find the Drain Currents ID1, ID2 of the matched transistors (M1 and M2), the input resistance Rin, output resistance Rout and the voltage gain AV of the circuit shown in Fig. 1, assuming NMOST with (VT = 0.6 V, μnC0 X = 200 uA/V2, W = 4 u and L = 0.8 u ) and R = 25 K. Fig. 1 ID1 = 0.08 mA, ID2 = 0.08 mA, Rin = 2.8 K, Rout = 10 K and AV = −8 ID1 = 0.8 mA, ID2 = 0.8 mA, Rin = 2.8 K, Rout = 10 K and AV = −16 ID1 = 0.08 mA, ID2 = 0.08 mA, Rin = 2.8 K, Rout = 10 K and AV = −4
For the ECL circuit in Fig. 1, the transistors exhibit VBE of 0.7 V at an emitter current I = 0.3 mA, R = 2 K, and have very high β. Find VB, VOH and VOL. VB = −1 V, VOH = −0.7 V and VOL = −1.3 V VB = −1.3 V, VOH = −0.7 V and VOL = −1.9 V VB = −1.2 V, VOH = −0.7 V and VOL = −1.7 V VB = −1.1 V, VOH = −0.7 V and VOL = −1.5 V
The saturation current equation of the MOSFET can be obtained from the linear current equation when The voltage between the drain and source VDS becomes equal to the saturation voltage VDS, Sat. The voltage between the drain and source VDS becomes equal to the threshold voltage VT. The voltage between the drain and source becomes VDS equal to voltage between the gate and source VGS. The voltage between the drain and source VDS becomes equal to (VGS + VT).
When the voltage across the drain and the source (VDS) is increased from a small amount assuming that the NMOS transistor is working in linear region, then the depth of the channel in NMOS transistor Will become non uniform and will take a tapered shape with deepest depth at the drain Will become non uniform and will take a tapered shape with deepest depth at the source Will remain uniform but the width of the channel will increase Will remain uniform but the width of the channel will decrease
The MOSFET in the following circuit is in which configuration? Common Source (CS) Common Drain (CD) Common Gate (CG) None of the mentioned
For NMOS transistor, at channel pinch off The depth of the channel at the Drain becomes zero and the current saturates. The depth of the channel becomes non linear The width of the channel becomes very large (resulting in very large resistance and very low, practically zero, current) The depth of the channel at the Drain becomes zero and the MOS transistor enter the linear region.
For the emitter-follower circuit shown in Fig. 1, the BJT used is specified to have β = 200. find: the DC current IE, the input resistance Rin and the voltage gain AV. Fig. 1 IE = 5.5 mA, Rin = 60.3 k and Av = 0.8 IE = 2.4 mA, Rin = 27.3 k and Av = 0.6 IE = 4.2 mA, Rin = 50.3 k and Av = 0.7 IE = 5 mA, Rin = 55.3 K and AV = 0.75
Consider NMOS Inverter with enhancement-load having VT = 0.8 V, (W/L)1 = x, (W/L)2 = 0.5, μnCox = 35 uA/V2, and VDD = 5 V. Find the value of "X", NML and the power dissipated Pdiss if output voltage of the inverter VO = 0.1 V when Vi = 4.2 V X = 16, NML = 0.7 V and Pdiss = 0.1 mW X = 12.6, NM = 0.7 V and Pdiss = 0.735 mW X = 12.5, NM = 0.7 V and Pdiss = 0.75 mW X = 13, NML = 0.7 V and Pdiss = 0.8 mW
For the logic circuit shown in Fig. 1, Find average Static Power dissipation? Fig. 1 12.5 mW 25 mW 18.75 mW 6.25 mW
The dynamic power consumption of Logic gates varies with the of power supply voltage. Square Cube Linear fourth power
When a logic gate is deriving another logic gate, the conditions which must be satisfied for proper operation is VOH < VIH and VOL > VIL VOH < VIH and VOL < VIL VOH > VIH and VOL < VIL VOH > VIH and VOL > VIL
A CMOS logic gate consists of a pull-down network down network and a pull-up network. PMOS, NMOS NMOS, PMOS CMOS, PMOS NMOS, CMOS
Examine the circuit below: a) Given that for the D flip flops: Setup time = .5ns Hold time = .3 ns Tcq ranges from .6 ns to 1.2 ns and the following delays: AND gates = 1 ns XOR gates = 1.5 ns NOT gates = .7 ns How fast can the circuit be clocked? b) Does the circuit satisfy hold time constraints? c) If so, modify skew values in a way that would violate hold times. Otherwise, modify skew values to meet hold times.
Using Fourier properties and pairs find the Fourier transformation of x(t) if: Hint : rect (t/T)⟷TVsinc(Tω/2)
When balanced, the current in galvanometer of Wheatstone bridge is A) 1 B) 0 C) max D) min
What is the potential drop from point B to point D for the circuit shown in the figure? The battery is ideal, and all the numbers are accurate to two significant figures. A) 0.35 V B) 2.5 V C) 2.0 V D) 0.0 V
A wheatstone bridge A) Uses the null method of measurement in which no current is drawn from the power supply when the balance condition is reached. B) Is used to give precision measurements of unknown resistances and battery voltages. C) Carries the same current in two parallel branches when it is balanced
In a slide wire bridge A) the wire represents two resistors of the Wheatstone bridge. B) a greater sensitivity is attained when the galvanometer is placed in series with a resistor. C) a greater relative error aries when the balance occurs near the middle of the wire.
The below figure shows a BJT inverter circuit and its associated voltage transfer characteristic curve not drawn to scale. For the circuit below, determine the values of v1 and v0, respectively, corresponding to the point labeled (A) on the transfer characteristic. 0.2 V, 10 V 5 V, 10 V 0.2 V, 5 V 0.7 V, 2 V 0.7 V, 10 V
Find the output resistance of the circuit, Rout . MOSFET Parameters: Kp = 200 μA/V2 VTP = −1.0 V λp = 0 V−1 η = 0 (note η = gmb/gm) 5 KOhm infinity 56 KOhm 28 KOhm 0 Ohm
The references for the voltage and current at the terminal of a circuit element are as shown in the figure. The numerical values for v and i are 48 V and -12 A. (Figure 1) p = vi Calculate the power at the terminals. p = −580 Wp = −380 Wp = 320 Wp = 60 W
The references for the voltage and current at the terminal of a circuit element are as shown in the figure. The numerical values for v and i are 48 V and -12 A. (Figure 1) State whether the power is being absorbed or delivered by the element in the box. Power is being delivered by the element in the box Power is being absorbed by the element in the box Insufficient information Power is being blocked
The references for the voltage and current at the terminal of a circuit element are as shown in the figure. The numerical values for v and i are 48 V and -12 A. (Figure 1) p = vi Do the electrons gain or lose energy as they pass through the element in the box? Gain Loose Neither gain nor loose Insufficient information