Considering the source follower circuit, if the input voltage increase over time, plot Vin and Vout over time in two different cases (1) without considering the body effect (2) considering the body effect.
Common figure for questions 7-9 In the above figure the NMOS is considered a long-channel device that does not possess channel length modulation, DIBL and velocity saturation effects At t = 0, its gate is instantaneously raised to VDD from 0 determine the equivalent resistance of the NMOS transistor for the output capacitor going from VDD to VDD/2 for t > 0 Answer in kΩ s rounded upto 2 decimal places. Given: W = 10∗Wmin L = 10∗Lmin. Assume that the NMOS device remains in saturation region all through-out the discharge (from VDD to VDD/2) 1 point In the above figure the NMOS is considered a short-channel device that does not possess channel length modulation and DIBL but however it has velocity saturation effects. At t = 0, its gate is instantaneously raised to VDD from 0, determine the equivalent resistance of the NMOS transistor for the output capacitor going from VDD to VDD/2 for t > 0? Answer in kΩs rounded upto 2 decimal places Given: W = Wmin L = Lmin. Assume that the NMOS device remains in velocity-saturation region all through-out the discharge (from VDD to VDD/2) 1 pointIn the above figure the NMOS is considered a short-channel device that does not possess DIBL but however has channel length modulation and velocty saturation effects. At t = 0, its gate is instantaneously raised to VDD from 0, determine the equivalent resistance of the Nmos transistor for the output capacitor going from VDD to VDD/2 for t > 0? Answer in kΩs with a precision upto 2 decimal places Given: W = Wmin L = Lmin . Assume that the NMOS device remains in velocity-saturation region all through-out the discharge (from VDD io VDD/2)
Figure 1 shows the cascade current source. If VT = 0.7 V and KP = 50 μA/V2, calculate: i. Current across M2, lM2 ii. Current across M3, IM3 Figure 1 2. Cascode current sink is as shown in Figure 2. If λ = 0.4 V−1, VT = 0.7 V, K = 110 μA/V2 and (W/L)1 = (W/L)2 = 1, calculate rout of the circuit. Figure 2
Consider the MOSFET amplifier circuit below. Assume that the transistor is in saturation mode, ignore ro and a) Draw the small-signal circuit of the amplifier using the MOSFET pi-model and the T-model. b) Derive an expression for the voltage gain. c) Derive an expression for the overall voltage gain. d) Derive an expression for the current gain. e) Find the amplifier input resistance. f) Find the amplifier output resistance. g) Based on your results, does this circuit serve as a "good" voltage amplifier or as a "good" current amplifier? Explain.
An nMOS device has a gate oxide thickness of 100 Å, electron mobility μn = 90 cm2 /(V.s), threshold voltage VT = 0.70 V, and dimensions W = 5 μm and L = 0.25 μm. a. Determine the gate capacitance C8 and the device transconductance βn. b. Determine the region of operation and the current IDS when VDS = 2 V and for the three cases of VGS = 0.5 V, 1.5 V, and 3.5 V.
A transistor schematic diagram of a CMOS digital circuit consisting of four MOSFETs is shown in the following figure (Fig. 3.1). The truth table of the digital circuit is also given. Fig. 3.1 (a). Sketch the logic gate symbol of the digital circuit (Fig. 3.1)? (2 marks) (b). Sketch the transistor schematic diagram of the missing part of the logic circuit (Fig. 3.1). (4 marks) (c). Draw the physical layout with a minimal chip area for the missing part (Q3(b)) of the logic circuit (Fig 3.1). Make sure that all the IC layers are clearly labeled and the scalable CMOS design rules should be followed approximately. (9 marks) (d). Sketch a transistor schematic diagram of the same logic gate (Q3(a)) implemented in CMOS but with three inputs (VA, VB, and VC). (6 marks) (e). If only n-channel MOSFETs can be used to implement the digital circuit in Fig. 3.1, sketch a transistor schematic diagram of such NMOS implementation. (4 marks) Note: In Q3(b), Q3(d) and Q3(e) above, you must use standard circuit symbols and show the signal interconnections clearly with proper labels.
(a) Design the circuit in Figure P3.39 such that IDQ = 0.50 mA and VD = 1 V. The transistor parameters are Kn = 0.25 mA/V2 and VTN = 1.4 V. Sketch the load line and plot the Q-point. (b) Choose standard resistor values that are closest to the ideal designed values. What are the resulting Q-point values? (c) If the resistors in part (b) have tolerances of ±10 percent, determine the maximum and minimum values of IDQ. Figure P3.39
In the above NMOS NOR gate circuit RD = 1 kΩ and for both n-channel MOSFETs conduction parameter Kn = 2 mA/V2, threshold voltage VTN = 0.5 V. Remember that voltage swing for both inputs V1, V2 are in between 0 V to 2.5 V. Find the maximum power dissipation in mW. In this case, find the output voltage VO in V.
Consider the gain stage shown, where Ibias = 200 μA and all transistors have W/L = 20 μm/0.4 μm. μnCox = 270 μA/V2 VTN = 0.45 V, μpCox = 70 μA/V2, VTP = −0.45 VV′ = 12.5 V/μm. Given the transistor parameters for the 0.18 μm technology, a. (25 pts) Find the output Impedance Rout. (Hint: Rout = V′AL/Id) b. (25 pts) Find the gain from the differential input to the output, Vout/Vin.
Consider an NMOS whose G, S, D terminals are connected as shown in the figure below. Note that the voltage VGD is applied across the gate and drain and VGD = VG−VD. The threshold voltage of the MOSFET is Vth . First determine the MOSFET region of operation and then write the equation for IDS as a function of VDS and sketch the IDS−VDS curve, for: (a) VGD = 0 V; (b) VGD = Vth/2; (c) VGD = 2 Vth.
Consider the source follower circuit shown in Fig 1. State your answer in terms of gm, gmb, ro and RS. NMOS bulk is connected to ground (Don't ignore body effect). Assume that the transistor is already in saturation, with appropriate biasing done. Ignore all capacitors. a) (5 points) Calculate the small-signal voltage gain Av of this amplifier. Can the gain be larger than 1? What is the maximum gain if gmro≫1 and Rs→∞? b) (2 points) What is the input resistance looking into the gate of M1 as labeled on the schematic? c) (3 points) What is the output resistance looking into the source of M1 as labeled on the schematic? Figure 1
Figure Q3 shows the i−v characteristics curve of a n-channel MOSFET (NMOS). Which of the following statement(s) regarding NMOS are true? (There can be multiple answers.) (4 marks) (a) An NMOS biased in the saturation mode operates in region II. (b) The Q-point of an NMOS small-signal amplifier should lie in the saturation region. (c) An inversion layer of electrons is induced in the channel region when the gate-to-source voltage of an NMOS is smaller than the threshold voltage (vGS < VTN). (d) An NMOS has n-type substrate. Figure Q3
Consider the circuit below. Take VDD = 2.4 V, VTn = 0.7 V and VTp = −0.5 V. Assume that there is no body effect. Determine VOUT1 and VOUT2 for the values of VIN as as given below. Give your answer in a tabular form as in the question, and provide a generic explanation of how you have computed the different values.
CMOS inverter shown in below figure fabricated in a 0.25 μm process for which Cox = 6 fF/mm2, μnCox = 270 μA/V2, μpCox = 70 μA/V2, Vtn = −Vtp = 0.5 V and VDD = 1.8 V Given that the (W/L) ratios of the nMOS and pMOS transistors are (W/L)n = 2 and (W/L)p = 5, respectively. If the total load capacitance CL is 6.25 fF and propagation delay tPHL is ps. (Please give the answer to 2 decimal places) (1 mark) Answer: tPHL = ps (Please give the answer to 2 decimal places, e. g. 54.48)
A pull-up network of a CMOS logic circuit is depicted in below figure. It is given that the (WL) ratios of the nMOS and pMOS transistors of a matched inverter are (W/L)n = 1 and (W/L)p = 4, respectively. If worst case propagation delays, tpLH and tpHL of the CMOS circuit are approximately equal to those of the matched inverter, the (W/L) ratio of the nMOS of input C in the pull down network is . (1 mark) Note that the W/L ratios of all the nMOS transistors must be in integer and in smallest possible sizes. Answer: (Please answer in integer number, e. g. 10)