7.47. Assuming λ = 0, calculate the voltage gain of the circuit shown in Fig. 7.74. Explain why this stage is not a common-gate amplifier. Figure 7.74
Suppose the supply voltage rail (VDD) is 20% less noisy than the ground (which implies that output low is more noisy). We designed a logic circuit which has an abrupt transition between the logic levels (i. e. amplification/transition region width = 0 V) and a full output swing (VOH = VDD and VOL = 0 V) What should be the value for noise margin high (NMH) and noise margin low (NML) for this circuit to work correctly with this noise constraint? NML = 0.55 VDD; NMH = 0.45 VDD NML = 0.45 VDD; NMH = 0.55 VDD NML = 0.5 VDD; NMH = 0.5 VDD NML = 0.4 VDD; NMH = 0.6 VDD