Consider an n-channel MOSFET with tox = 9 nm, μn = 500 cm2/V⋅s, Vtn = 0.7 V, and W/L = 10. Find the drain current in the following cases: (a) vGS = 5 V and vDS = 1 V (b) vGS = 2 V and vDS = 1.3 V (c) vGS = 5 V and vDS = 0.2 V (d) vGS = vDS = 5 V PROBLEM 5.14, in Microelectronic Circuits (Sedra/Smith), 6th Edition.
A particular n-channel MOSFET is measured to have a drain current iD = 0.4 mA at vGS = vDS = 2 V, and iD = 0.1 mA at vGS = vDS = 1.5 V, what are the values of βn = μnCoxW/L and Vtn?
Q1. Consider the CMOS inverter of which the transistors have the following parameters: μnCox = 4μpCox = 160 μA/V2, ∣γ| = 0.5 V1/2, 2Φf = 0.5 V, λ = 0.001 V−1, Vtno = 0.6 V, Vtpo = −0.8 V, (W/L)n = 1 and (W/L)p = 4. The supply voltage VDD = 3.3 V. The capacitive load at the output node is 20 pF. The input voltage Vin is expected to be a perfect periodic square wave with full swing (low level : 0 V, high level: VDD). (a) Calculate tl, the time required for the output voltage Vout to change from 0 V to the threshold voltage of the inverter, using the average-current method. (b) Write the expression of calculation of t2, the time required for the output voltage Vout to change from 2.9 V to the 0.4 V, using the analytical method (integral). Then calculate t2 using the average-current method. (c) Determine the maximum frequency of the periodic square wave input so that the output signal will have a full swing in each cycle. (d) Calculate the peak value of in, the NMOS transistor current, during the transition, and its average value over a clock cycle T. (The average value here is not the same as the average-current in the "average-current method" for delay estimation) (e) If the capacitive load is now changed to be 250 pF, what can be done to make tl and t2 unchanged?
Q2. Consider a single-NMOS switch connecting an ideal voltage source of 3.3 V and a capacitor load of 25 pF that is empty initially (at t = 0). The gate voltage of the transistor changes from 0 V to 3 V at t = 0 and remains at the 3 V level from the moment t = 0+on. Estimate the time required for the voltage across the capacitor to change from 0.1 V to 1.8 V. The parameters of the NMOS transistor are the same as that in Q1, and (W/L)n = 1.
Q3. Consider the pseudo-NMOS inverter of which the transistors have the following parameters:μnCox = 4μpCox = 160 μA/V2, ∣γ| = 0.5 V1/2, 2Φf = 0.5 V, λ = 0.001 V−1, Vtno = 0.6 V, Vtpo = −0.8 V, and (W/L)p = 1. The supply voltage VDD = 3.3 V. The capacitive load at the output node is 20 pF. The input voltage Vin is expected to be a perfect periodic square wave with full swing (low level : 0 V, high level: VDD). (a) Determine (W/L)n so that the low voltage level of the output signal Vo will not higher than 0.4 V. (b) Based on the result of (a), calculate the static current of the circuit when Vi = VDD. (c) Based on the result of (a), estimate the time required for Vo to change from 0.8 VDD to 0.2VDD.
In the following exercises, we have μnCox = 4μpCox = 160 μA/V2, ∣γ| = 0.5 V1/2, 2Φf = 0.5 V, λ = 0.001 V−1, Vtno = 0.6 V, Vtpo = −0.8 V, and VDD = 3.3 V. Q2. (a) Sketch the circuit diagram of a CMOS gate for the function y = a + b + cd. (b) Assume that the transistors in the gate design in (a) are all sized as W/L = 1 μm/1 μm, and the capacitive load of the gate is 10 fF. Estimate the rise time and fall time of the gate. The worst-case condition should be considered. Q3. (a) Sketch the circuit diagram of a pseudo-NMOS gate for the function y = a + b + cd. (b) Assume that the transistors in the gate design in (a) are all sized as W/L = 1 μm/1 μm Determine the low-level output voltage under the worst-case condition. (c) Estimate the tpHL under the worst-case condition, assuming that the capacitive load of the gate is 10 fF.