Q5. In the CMOS op amp shown below, all MOS devices have |Vt| = 1 V, μnCox = 2μpCox = 200 μA/V2, and |λ| = 0.02 V−1. Device lengths and widths are indicated on the figure in units of μm. VDD = +5 V (Fig 5) (a) Design R to provide a 10−μA reference current. (b) Assuming vO = 0 V with vICM = 0 V, as established by external feedback, perform a DC bias analysis, find the voltages at nodes B and D. (c) Provide in table form, VGS,ID, gm and ro for all devices. (d) Estimate the voltage gain vo/vid of the amplifier. (e) What is the output signal range under no load condition?
The CMOS transmission gate shown has an input voltage of 2.0 V when it turns off. The W/L of the n -channel is 4 μm/0.6 μm and the W/L of the p -channel is 8 μm/0.6 μm. Estimate the change in output voltage due to clock feedthrough. You may assume the total parasitic capacitance between the output node and ground is 100 fF, that VDD = 3.3 V, and that the clock signal changes very fast. The overlap capacitances for PMOS and NMOS devices are approximately Cgs-ov = Cgd-ov = 1.7 x 10−4 pF/μm. Assume, VTN0 = 0.7 V, VTP0 = −0.8 V, Cox = 3.4 fF/μm2.
In the amplifier circuit of figure below, Q2 and Q3 are matched. kn(W/L)n = kp′(W/L)p = 8 mA/V2, and all transistors have |Vt| = 0.5 V and |VA| = 5 V. Give units of gm as mA/V. The signal vsig is a small sinusoidal signal with no dc component. a) What type of amplifier, is this? b) Neglecting the effect of VA, find the dc drain current of Q1, ID , and the required value of VBIAS, . c) Find the values of gm1 and ro1 , r02 , and ro3 . (units: mA/V, kohms) d) Find the values of Rin and Rout e) Calculate the voltage gains vo/vv, A1 , and vo/vsig, A f) How large can vsig be (peak-to-peak), , while maintaining saturation-mode operation for Q1 and Q2?