Consider the shown circuit, where R = 500 Ω, L = 40 μH, C = 30 nF, and Vs is a sinusoidal source with a peak amplitude of 5 V. (Vs(t) = 5 cos(ωt)V) Part 1: Hand Calculation a) Assume the source has a frequency of 140 kHz, calculate: the impedance Z seen by the source (expressed as a complex number and as magnitude/phase). Is the impedance capacitive or inductive? the source current Is. (Expressed as a Phasor and as a time function)the voltage Vo (Expressed as a Phasor and as a time function) b) Repeat part (a) at a frequency of 148 kHz c) Calculate the resonant frequency of the circuit (the frequency at which the reactive components cancel each other) d) find the impedance of the circuit at the resonant frequency e) Calculate the Quality factor and the 3-dB bandwidth of the circuit. Note that the resonator (LC circuit) is parallel Part 2: Simulation Draw the circuit on LTSpice a) Perform AC analysis (from 130 kHz to 170 kHz, use linear scale with 10000 points) and plot the following on a separate plot: The voltage (Vo)The current (Is)The impedance seen by the source b) From the plots verify your results in the hand calculation for parts (a) and (b) c) from the plots find the resonant frequency d) From the voltage plot, find the 3-dB bandwidth. Notes: The default Y-scale for AC analysis in LTSpice is dB, you can change it to linear To plot the impedance, add a trace and plot the expression of V over I Homework submission is through the Moodle platform Submit a single compressed file containing: The hand calculations Screenshot showing the circuit and the simulation results The schematic file (.asc)The netlist file (.net)
Problem 3 (2 pt) In the triode region of operation, we can approximate the drain current to drain voltage relationship as linear over a limited voltage range (using a resistance value taken from the slope of the ID VDS curve), but the full curve is actually quite nonlinear. If we want the transistor to look like a 1 KOhm "resistance" at VDS ≈ 0, what gate voltage should we use? For this problem use an nFET with kn′ = 25 uA/V2, W/L = 5, Vt = 0.9 v.
VDD = VSS = 1.5 V, μpCox = 250 μA/V2, μn = 2.5⋅μp, V thn = 0.5 V, Vthp = −0.5 V, λn = λp = 0.1 V−1 is given for the circuit below. The differential amplifier biased using current mirrors will be designed to meet the following requirements: Adm = −70, IREF = 150 mA, Vov3 = Vov4 = Vov5 = Vov6 = Vov7 = 150 mV. a) Calculate the value of resistor R and the W/L values of the transistors. b) Calculate the value of CMRR
In the circuit below, the supply voltage is VDD = 2.5 V and the MOS transistors have process transconductance parameters μnCox = 0.3 mAV2 and μPCox = 0.2 mAV2, threshold voltages Vtn = −Vtp = 0.4 V, channel-length modulation coefficients λn = −λp = 0.1 V^−1, and channel lengths L1 = L2 = 0.2 μm. (a) Choose the widths of the transistors, W 1 and W 2, and the gate bias voltages, VG1 and VG2, such that the dc output voltage be Vo = VDD/2 and all transistors operate in saturation with an overdrive voltage of 0.5 V and a drain current of 85 μA. (b) Find the small-signal voltage gain vo/vi. Calculate the largest peak-to-peak amplitude of the input sinusoid vi and the corresponding amplitude of the output sinusoid vo that the circuit can handle while all transistors remain in saturation region.