A conducting bar of mass m = 0.550 kg is moving at velocity v0 = 1.60 m/s on two frictionless wires that are L = 4.20 m apart and connected by a resistor, R. The bar starts out with x0 = 10.0 m between it and the resistor. A magnetic field B = 6.00 T points out of the screen. What maximum value must R be so that the bar stops before hitting the resistor? 1000, answer in Ohms; 3 sig figs. B out of screen
Consider the following single-stage MOSFET amplifier circuit with an enhancement mode NMOS MOSFET, assuming all external capacitors have infinitely large capacitance values. Is is ideal current source. a) What is the type of this amplifier? Calculate the DC operating point current and voltages (IDS, VDS) for this amplifier and determine the mode of operation of the MOSFET. b) Calculate the transconductance gain (gm) and the output resistance (ro) of the MOSFET at the operating point. c) Draw the small-signal ac equivalent circuit of the amplifier. d) Find the symbolic expression for the small-signal voltage gain of the amplifier, vout /vsig , and calculate its value. Show your work clearly. e) Find the expressions for the input resistance (Rin ), the output resistance (Rout ) of the amplifier and calculate their values. Show your work clearly. f) Calculate the small-signal input range of the amplifier for linear amplification. Show your work clearly.
**13.101. The drain resistors RD in Prob. 13.90 are replaced with PMOS transistors as shown in Fig. 13:31(a). (a) What is the required value of Kp for these transistors? (b) What is the voltage gain of the new amplifier? (c) What was the original voltage gain? (a) (b)
A two-stage amplifier is shown below. The parameters of the MOSFETs are given in the text box next to the circuit diagram. The biasing current sources both have small signal shunt resistances of 200 kΩ. MOSFET Parameters |M1| = |M2| = |M3| = |M4| Vt = 1 V; VA = 50 V; kn = kp = 4×10−4 A/V2 M5 kn = 10−3 A/V2; Vt = 1 V; VA = 50 V a) Determine the differential gain Ad = Vo/(Va−Vb). b) Determine the common mode rejection ratio, CMRR. For this circuit Acm = Vo/{(Va+Vb)/2}.
We can make a differential pair amplifier with PMOS input devices as shown below. Suppose circuits are completely symmetric (RDS are equal, M1,2 are similar, and each tail current source requires minimum of Vod to operate) a) What is the single-ended and differential output swing? b) Draw DM and CM half-circuits. (assume that the tail current source has an output impendence of RSS) c) Calculate DM and CM gains. d) What is the acceptable input CM range? e) Compare the results from (d) with the NMOS diff pair we studied in the class. For the rest of HW assume: VDD = 1 V, Vth = 0.3 V, μnCox = 200 μAV2, λ = 0.2 V−1, γ = 0. *All the differential amplifiers are symmetric unless we specifically said that we are interested in analyzing mismatch effects in a problem.
[25%] In the following Domino logic circuit, VDD = 2 V. There are parasitic capacitances of 10 fF, 10 fF, 40 fF, 20 fF and 60 fF at nodes 1, 2, 3, 4 and Y, respectively. All the NMOS transistors have an ON -resistance of 10 kΩ and a threshold voltage of 0.43 V. (a) Express X and Y as Boolean functions of inputs A, B, C, D, and E. (b) The CMOS inverter between the two dynamic gates is essential. Why? (c) How would you set the relative driving strength of the NMOS and PMOS in this inverter? Explain. (d) Consider A = B = 1 and C changing from 0 to 1 during the evaluation phase (clk is high). Estimate the propagation delay from C to node 3 using the Elmore model. (e) The above inputs come together with E = D = 0, and node 4 is initially discharged. What is the voltage at Y at the end of the evaluation phase?
For the RLC circuit shown, the switch is initially in the open position and closes at time t = 0. The component values are R = 77 kΩ, L = 61 mH, C = 578 nF, and the source current is Is = 128 μA. Assuming there is no initial energy in either the capacitor or the inductor (at time t = −∞), What is the value of the inductor voltage in the circuit at time t = 0+? Enter your answer in units of Volts.
Charge of uniform volume density ρ = 1.6 nC/m3 fills an infinite slab between x = −4.8 cm and x = +4.8 cm. What is the magnitude of the electric field at any point with the coordinate (a) x = 4.3 cm and (b) x = 8.2 cm? (a) Number Units (b) Number Units
For the circuits shown in Fig. 1, plot Vo1, Vo2, Vo3, and Vo. Period of the clock is 20 ns. Device resistance is less than 1 kΩ for VGS > VTH and VTH = 0.5 V. Vo1, Vo2, Vo3, and Vo are loaded with capacitance of 0.1 pF. Vdd = 2 V. [9+6] (a) (b)
1. (30) Consider the MOSFET amplifier of the following figure. (λ = 0) 1) Draw the small signal equivalent circuit with T-model. (Show all the parameters) 2) Derive the input resistance (Ri) 3) Derive the output resistance (Ro) 4) Derive the overall voltage gain (vo/vi)
In the figure, an ac generator with emf E = Emsinωdt, where Em = 25.4 V and ωd = 381 rad/s, is connected to a 12.3 H inductor. (a) What is the maximum value of the current? (b) When the current is a maximum, what is the emf of the generator? (c) When the emf of the generator is -12.2 V and increasing in magnitude, what is the current?
In the figure ε = 13.4 V, R1 = 2770 Ω, R2 = 3320 Ω, and R3 = 4950 Ω. What are the potential differences (in V) (a) VA − VB, (b) VB − VC, (c) VC − VD, and (d) VA − VC? (a) Number Units (b) Number Units (c) Number Units (d) Number Units
Capacitor 3 in Figure (a) is a variable capacitor (its capacitance C3 can be varied). Figure (b) gives the electric potential V1 across capacitor 1 versus C3. The horizontal scale is set by C3 s = 13 μF. Electric potential V1 approaches an asymptote of 10 V as C3 approaches infinity. What are (a) the electric potential V across the battery, (b) C1, and (c) C2? (a) (b) (a) Number Units (b) Number Units (c) Number Units
Please identify the status of the MOSFETS in the following amp Vin = Vin1 − Vin2 , Vout = Vout1 − Vout2 . V thp = −0.5 V, V thn = 0.5 V, Vb = 2.4 V, VDD = 3.3 V, and Vin1 = Vin2 = 2 V, after measurement, we found that Vc = 1.1 V, and Vout1 = Vout2 = 1.8 V. Please identify the status of the MOSFET M1-M4, including if it is turned on, and which operating region (triode or saturation) it belongs to.
For the circuit shown in Fig. 1, plot Vour. Period of the clock is 20 ns. Device resistance is less than 1 kΩ for VGS > VTH. Vour is loaded with capacitance of 0.1 pF. Vdd = 2 V. [10] Fig. 1
Find the biasing current and output voltage of the following circuit (10 points) and identify the voltage gain of the circuit (Vo/Vid)(20 points) Vth = 0.5 V, Vdd = 2.5 V VBEON = 0.7, μcoxW/L = 0.1 A/V2
Consider the p-channel MOSFET (M1) shown in the left figure below. Which region is it operating in? If W/L = 20, μpCox = 100 μA/V2, VT = -0.4 V, calculate the drain current. Note that the source is the terminal with the arrow. In a PMOS FET, VDS and VGS are negative. The circuit symbol for a PMOS FET is shown below (right). Hint: You can assume that the FET is operating in saturation and then find VD. After finding VD, verify saturation condition is met. If it satisfies the saturation condition, then the assumption in justified.
Please use the 180 nm process parameters shown at the end of homework for all the homework questions. For NMOS as Rn = 6.47 KΩ, for PMOS as Rp = 29.6 KΩ, and C1 = 0.89 fF)Design the static complementary gates (CMOS gates) for the following logic expressions using pull-up/pull-down networks. Use a truth table to show logical equivalence for converted expressions. Assume inverted variables are available, i. e., you do not have to add inverters for complementary variables. (10 pt) a) a+b b) ab c) (a+b)c d) (ab)′+(cd)
Size the transistors in each of those gates so that its pullup and pulldown times are approximate equal. Assume effective resistances for NMOS as Rn = 6.47 KΩ, for PMOS as Rp = 29.6 KΩ. The loading capacitance for the network is CL. Please show all the steps. Please consider the following two cases: (15 pt) (1) In the worst case (2) In the best case a) f = a′b′c′+d′ b) f = a′b′+c′d′ c) f = a′b+bc
Compute transition times for a four-input NAND gate with 8 /2 pulldown (the W/L = 8/2 for n-type transistors) and 8/2 pullup that drives an identically-sized NOR four-input gate (the NAND gate only drives one input of the NOR gate): (10 pt) a) Rise time b) Fall time
For a metal 1 wire with Rint = 500 ΩCint = 200 fF, which is driven by a minimum-size buffer, which has equivalent resistance R0 = 6.47 kΩ and input capacitance C0 = 1.78 fF. The wire then drives another minimum-size buffer as shown below. (20 pt) (a) If no additional buffer is inserted, then what is 50% delay? (b) If one buffer is inserted and the wire is evenly divided into 2 sections (k = 2) and all buffer inserted are minimum-size buffers (h = 1), what is 50% delay? (c) If one buffer is inserted and the wire is evenly divided into 2 sections (k = 2) and all buffer inserted are two times of minimum-size buffers (h = 2), what is 50% delay? (d) What is optimal number of buffers, buffer size, and minimum 50% delay?
13.84. (a) What are the Q-points of the transistors in the amplifier in Fig. P13.84. if VCC = 20 V, VEE = 20 V, I1 = 200 μA, I2 = 400 μA, I3 = 1 mA, βF = 100, and VA = 50 V? (b) What are the differential-mode voltage gain and input resistance? (c) What is the amplifier output resistance? (d) What is the common-mode input resistance? (e) Which terminal is the noninverting input?
9.68. The common-gate stage of Fig. 9.83 employs the current source M3 as the load to achieve a high voltage gain. For simplicity, neglect channel-length modulation in M1. Assuming (W/L)3 = 40/0.18, λn = 0.1 V−1, and λp = 0.2 V−1, design the circuit for a voltage gain of 20, an input impedance of 50 Ω, and a power budget of 13 mW. (You may not need all of the power budget.) Figure 9.83
Unless otherwise stated, assume that VCC = 10 V, VEE = -10 V and that βn = 200. The diode is a standard silicon diode. You may use the constant voltage drop model for any pn-junctions. a. If Vin = 3 V, what is Vout? b. If Vin = 3 V, and VCC = 1 V, what is Vout? What is the status of every pn-junction in the circuit? (Don't forget the diode). c. If Vin = 3 V, VCC = 10 V, and VEE = 0 V, what is the collector current of the BJT? What is the current through the diode? How do these quantities compare with the same values for part (a)?
*7.9 Figure P7.9 shows an amplifier in which the load resistor RD has been replaced with another NMOS transistor Q2 connected as a two-terminal device. Note that because vDG of Q2 is zero, it will be operating in saturation at all times, even when vI = 0 and iD2 = iD1 = 0. Note also that the two transistors conduct equal drain currents. Using iD1 = iD2, show that for the range of v1 over which Q1 is operating in saturation, that is, for Vt1 ≤ vI ≤ vO+Vt1 the output voltage will be given by vo = VDD − Vt + (W/L)1(W/L)2 Vt − (W/L)1(W/L)2 vt where we have assumed Vt1 = Vt2 = Vt. Thus the circuit functions as a linear amplifier, even for large input signals. For (W/L)1 = (50 μm/0.5 μm) and (W/L)2 = (5 μm/0.5 μm), find the voltage gain. Figure P7.9
For the given circuit, assume that v(t) is a sinusoidal signal with a frequency of 10 MHz and amplitude of 3 V. a) Find the current i(t) b) Write the phasors of v(t) and i(t) c) find the instantaneous power (as a time expression) consumed by the capacitor d) find the average power consumed by the capacitor