Q (100p):For the given circuit, V+ = 15 V, V− = −15 V, I1 = I2 = 0, 5 mA. R1 = R2 = 2 MΩ where R1 is the internal resistance of l1 current source and R2 is the internal resistance of I2 current source. Current gain of Q3 transistor is β = 80. VBE = 0.7 V, VA = 75 V and VT = 25 mV. M1 and M2 are identical MOSFETs where KP = μpCox(W/L) = 5 mA/V2 and VTP = −1 V. Considering DC conditions, VODC = 0 V. a) Calculate RD and the operating points of M1, M2 and Q3 transistors considering λ = 0 and ignoring base current of Q3 transistor. (30p) b) Draw mid-frequency small signal equivalent circuit. (You should add output resistance of Q3 to equivalent circuit.) (30p) c) Derive the expression of voltage gain v0/(v1 − v2) and calculate its value. (You should include the value of output resistance of Q3 in your calculations.) (40p)
The transistors shown in the figure below are biased in saturation. Transistor Mi has its transconductance and output resistance as gmi and roi respectively. Derive the small signal impedance seen into the output terminal. If you are splitting the circuit into different parts then show analysis of each part.
Problem 2. A. Design the simplest dynamic CMOS logic gate that implements the function Y = A⋅B+BC+C⋅D+C― B. Size the PDN for matching a reference inverter with (W/L)n = 0.27 μm/0.18 μm C. Knowing VDD = 1.8 V, Vtn = −Vtp = 0.5 V, μnCox = 3 μpCox = 300 μA/V2 and the load capacitance CL = 20 fF. i. Design the Precharge PMOS transistor such that when V0 = 0.1 VDD the precharge current Ip = 190 μA. ii. In a Precharge sequence, the output is initially zero. Calculate the rise time of the output voltage (time for Vo to reach 0.9 VDD starting at 0.1 VDD). iii. Determine the maximum allowed clock frequency knowing that the clock has to satisfy the following conditions : a. Remain ON during the output voltage rise time (caculated in ii.) b. Remain OFF during the longest evaluation period of the Low state (2 tpHL).
5.11 A p-channel MOSFET with a threshold voltage Vtp = -0.7 V has its source connected to ground. (a) What should the gate voltage be for the device to operate with an overdrive voltage of |VOV| = 0.4 V? (b) With the gate voltage as in (a), what is the highest voltage allowed at the drain while the device operates in the saturation region? (c) If the drain current obtained in (b) is 0.5 mA, what would the current be for VD = −20 mV and for VD = −2 V?
Consider differential amplifier circuit shown below where all the transistors are fabricated in such a way that the |VAp| = VAn = 3.6 V (early voltages for PMOS and NMOS transistors). Note: early voltage of MOS transistor is given by VA = ID×r0. Similarly, μn. Cox = 100 μA/V2, μp. Cox = 25 μA/V2 and all the transistors involved in this circuits operate with same overdrive voltage Vov of 0.5 V. Determine the W/L ratios (sizes) of all the transistors and the differential gain of the circuit. {10 marks}
Circuitry for the active-loaded MOS-differential amplifier with matched Q1 and Q2 saturated transistors is shown below. Differential gain of this amplifier is 80 V/V and assume that Iref = I = 100 μA. Similarly the values of μn⋅Cox = 3×μp⋅Cox = 90 μA/V2; threshold voltage values are Vtn = |Vtp| = 0.7 V and VAn = |VAp| = 20 V (Note: early voltage of MOS transistor is given by VA = ID×r0). In addition, DC voltage at the gates of Q6 and Q3 is +1.5 V whereas at the gates of Q7, Q4 and Q5, the DC voltage is -1.5 V. In order to satisfy the above design specifications, please determine the values of resistance ' R ' and W/L ratios of all the transistors. Additionally, determine the drain current ID and VGSn or VGSp for all the transistors of the circuitry shown below. {20 marks}
In the following CMOS inverter logic gate, assume the transistor size of (W/L)n = 0.8 μm/0.20 μm and (W/L)p = 1.6 μm/0.20 μm and VDD = 3.0 V. (a). Determine the operation modes (e. g. cut-off, linear or saturation) of the NMOS and PMOS transistors respectively at Vin = 0.2 V, 0.9 V, 1.5 V, 2.1 V, and 2.8 V. Using a table to list the operation modes is recommended. (Note: You may need to do multiple calculations for the data point Vin = 1.5 V with Vin = 1.4 V or 1.6 V). (b). Using the tabulated results in (a) or otherwise, determine the current flowing through both the NMOS and PMOS transistors at the different input voltage Vin in (a). (c). Using Matlab or Excel, plot a graph of the current against the input voltage Vin. (d). Using the above results in (a) and (b) or otherwise, determine the output voltage Vout at the different input voltage Vin in (a). (e). Using Matlab or Excel, plot a graph of the voltage transfer characteristics (VTC) (i. e. output voltage Vout versus input voltage Vin ) of the CMOS inverter with the five sets of data points obtained. It is given that the threshold voltage VTon = 0.50 V and μnCox = 430 μA/V2 for the NMOS transistor while VTop = −0.50 V and μpCox = 210 μA/V2 for the PMOS transistor. Assume the long-channel approximation of the MOSFET and there is no body effect (i. e. the body terminal of the MOSFETs are properly connected respectively to ground and VDD).
The differential amplifier depicted in the following figure employs two current mirrors to establish the bias for the input and load de-vices. Assume W/L = 10 μm/0.18 μm for M1 M6. The input CM level is equal to 1.2 V. (a) Select (W/L)7 so as to set the output CM level to 1.5 V. (Assume L7 = 0.18 μm.) (b) Determine the small-signal differential gain of the circuit. (c) Plot the differential input/output characteristic.
Problem F Determine all sets of MOSFET parameters below that would result in the 200 Ohm load getting at least 90% of the supply voltage when the AND gate, which has VOH(min) = 2.4 V, has a high output. a. VT = 1.6 V, rDS(on) = 22 Ohms b. VT = 2.6 V, rDs(on) = 10 Ohms c. VT = 1 V, rDS(on) = 15 Ohms d. VT = 5 V, rDS(on) = 25 Ohms
Q5. [1.5 marks] For the following circuit, assume that at the frequencies of interest all the device parasitic capacitances can be ignored. Also, assume: λN = λP = 0, and Y = 0, VDD = 1.8 V, Ibias = 50 μA, VTN = |VTP| = 0.4 V, μnCox = 1 mA/V2, μpCox = 0.5 mA/V2, (W/L)0 = 32, (W/L)1 = 16, (W/L)2 = 16, (W/L)3 = 32, RD = 1 kΩ, Vbias1 = 0.65 V, and Vbias3 = 1.15 V. (a) Find the minimum required Vbias2. (b) What is the small-signal voltage gain of the circuit? (c) Calculate input and output impedance of the circuit.
The NMOS transistor below has Vt = 0.6 V, and VA = 5 V which means channel effect is considered. The dc voltage at the source is measured as -0.8 V. Assume all three capacitors to be ideal (infinite large). Here RD = 9 kohms and RG = 20 Mohms (a) What is the dc voltage at the drain terminal? (b) What is the overdrive voltage at which the transistor is operating? (c) What is the region in which the MOSFET is operating? (d) Find the values of gm and r0. (e) Now assume Y is connected to ground and a small signal vX is at X, find the input resistance Rin and overall voltage gain vx/vz. Please round overall voltage gain Gv to the nearest two decimal places.
1. (18 points total) In the circuit shown below, the PMOS transistor has Vtp = −0.8 V, VA = −28 V, and operates with VD = 3 V. Note the 22 MΩ gate resistor, which is another way to bias a CS stage, used here in addition to the current source. You may assume that any channel length modulation does not appreciably affect the DC biasing. (a) Draw the small-signal equivalent circuit for this transistor amplifier. Be sure to label the input and output voltages as well as the source, gate and drain locations on the schematic. Calculate all parameters/component values used in your equivalent circuit that were not given in the problem. (6 points) (b) What is the input resistance of the amplifier? What is the output resistance? (6 points) (c) What is the voltage gain Av = vo/vi? How much does your calculation change if you assume RG → ∞? (6 points)
Based on the circuit in FIGURE Q3a, design the current mirror which exhibits an output current, Io = 90 μA for a variable resistor ranging from 0 to 15 kΩ. Assume the following parameters, L1 = L2 = 1 μm, μnCox = 180 μAN2, Vt = 0.4 V and λ = 0. Decide the minimum values for the transistor widths, which will be able to meet these specifications. Now, find the small-signal output resistance of the current mirror by assuming a biasing value of 0.65 V, for λ = 0.1 V−1 for transistors M1 and M2. [15 marks]