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10.13 A CMOS inverter fabricated in the process specified in Problem 10.12 utilizes a p-channel device four times as wide as the n-channel device. If the VDD supply is subject to very-high-frequency noise and there is an equivalent load capacitance of 1 pF, what is the 3-dB cutoff frequency embodied in each gate for this supply noise?

10.13 A CMOS inverter fabricated in the process specified in Problem 10.12 utilizes a p-channel device four times as wide as the n-channel device. If the VDD supply is subject to very-high-frequency noise and there is an equivalent load capacitance of 1 pF, what is the 3-dB cutoff frequency embodied in each gate for this supply noise?

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10.13 A CMOS inverter fabricated in the process specified in Problem 10.12 utilizes a p -channel device four times as wide as the n -channel device. If the V D D supply is subject to very-high-frequency noise and there is an equivalent load capacitance of 1 p F , what is the 3-dB cutoff frequency embodied in each gate for this supply noise?

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