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(10%) Please explain your answers clearly to the following questions. (a) Explain the concept of channel length modulation in NMOS and demonstrate its corresponding equation for drain current (IDs). (2%) (b) Elaborate on the body effect phenomenon in NMOS and present its corresponding equation for threshold voltage (VTH). (2%) (c) Write down the NMOS drain current equations for both the linear and saturation regions. ( 2% ) (d) Illustrate the complete small-signal model for NMOS, including all the capacitance terms. (4%)

(10%) Please explain your answers clearly to the following questions. (a) Explain the concept of channel length modulation in NMOS and demonstrate its corresponding equation for drain current (IDs). (2%) (b) Elaborate on the body effect phenomenon in NMOS and present its corresponding equation for threshold voltage (VTH). (2%) (c) Write down the NMOS drain current equations for both the linear and saturation regions. ( 2% ) (d) Illustrate the complete small-signal model for NMOS, including all the capacitance terms. (4%)

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  1. ( 10 % ) Please explain your answers clearly to the following questions. (a) Explain the concept of channel length modulation in NMOS and demonstrate its corresponding equation for drain current (IDs). ( 2 % ) (b) Llaborate on the body effect phenomenon in NMOS and present its corresponding equation for threshold voltage ( V T H ) . ( 2 % ) (c) Write down the NMOS drain current equations for both the linear and saturation regions. ( 2 % ) (d) Illustrate the complete small-signal model for NMOS, including all the capacitance terms. (4%)

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Q3. An n-channel MOSFET (nMOSFET) is connected as shown in the circuit in Fig. Q3. A drain current (ID) equal to 3.2 mA is measured with the supply voltage VSS = 0 V. When VSS is changed to −1 V, the threshold voltage of the nMOSFET changes by 0.258 V (as compared to the threshold voltage when VSS = 0 V ) and the drain current is reduced to 2.8 mA. [Hint: The MOSFET drain current equations are applicable even if V/ ss is not 0 V. Fig. Q3 (a) When VSS = −1 V, does the nMOSFET experience body effect? Why? (2 marks) (b) Which region is the nMOSFET operating in? Why? (3 marks) (c) Calculate the threshold voltage VTH when VSS = −1 V. Neglect channel length modulation. (6 marks)

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(21 pts total, 3 pts each) Determine the operating region and drain current for the following transistors. If the transistor is in saturation or triode, determine the drain voltage which is the boundary between those two regions. If the transistor is in cutoff, determine the gate voltage which is the edge of cutoff. The channel length is the minimum value. The NMOS width is 0.90 μm and the PMOS width is 1.8 μm. The channel length is 0.18 μm in all cases. Numerical answers to check your work: (a) drain voltage boundary = 0.727 V, ID = 295 μA (e) drain voltage boundary = 1.10 V, ID = 234 μA (a) (b) (c) (d) 0.6 V 1.0 V (f) (g)

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Assumptions for all problems (unless specified otherwise, give answers to 10% ): VDD(V) VT0( V) Body effect γ(V 0.5 ) VDSAT( V) k’ (A/V 2) λ(V -1 ) NMOS 2.0 0.4 0 0.5 500×10-6 0 PMOS -0.4 0 -0.5 -200×10-6 0 1. All transistors have the minimum length (Lunit = 250 nm) 2. Ignore body effect and channel length modulation 3. A transistor's intrinsic capacitance (cap) and gate cap are equal, i.e., Cint = Cg, γ = 1 4. The unit-sized transistor has Wunit = Lunit and intrinsic cap Cint = Cg = Cdb = Csb = 1.0fF. 5. For the unit sized inverter, β = (W/L)P / (W/L N = WP/WN = 2, WN = L = 250 nm 6. The unit sized transmission gate has a resistance Req,tr = 10kΩ and all caps of 1.0fF. a) (6 pts) How does the following circuit operate? In a few words/charts, describe what it does Sketch the waveforms of nodes X and Q given the inputs shown below. Initial state of signals X and Q are unknown (mark with xxx as needed) until the impact of the input signals propagate. X Q b) (4 pts) How would you size each transistor? Match the 2:1 inverter (including the clock). Draw the sizing next to the schematic. Calculate the switch model equivalent resistance(s) (note the equation given at the front of the exam for Req, switch model capacitance(s) (based on your sizing), and worst-case propagation delay through the circuit, max(tpLH,tpLH), where output is taken from Q and inputs are IN1 and IN2. c) (4 pts) Calculate the energy consumption from the VDD power supply of this circuit for the input pattern and time duration given in the timing diagram (previous page). Ignore the energy consumption related to driving IN1, IN2, and CLK. State any assumptions you need to make to determine a numerical value.

Assumptions for all problems (unless specified otherwise, give answers to 10% ): VDD(V) VT0( V) Body effect γ(V 0.5 ) VDSAT( V) k’ (A/V 2) λ(V -1 ) NMOS 2.0 0.4 0 0.5 500×10-6 0 PMOS -0.4 0 -0.5 -200×10-6 0 1. All transistors have the minimum length (Lunit = 250 nm) 2. Ignore body effect and channel length modulation 3. A transistor's intrinsic capacitance (cap) and gate cap are equal, i.e., Cint = Cg, γ = 1 4. The unit-sized transistor has Wunit = Lunit and intrinsic cap Cint = Cg = Cdb = Csb = 1.0fF. 5. For the unit sized inverter, β = (W/L)P / (W/L N = WP/WN = 2, WN = L = 250 nm 6. The unit sized transmission gate has a resistance Req,tr = 10kΩ and all caps of 1.0fF. a) (6 pts) How does the following circuit operate? In a few words/charts, describe what it does Sketch the waveforms of nodes X and Q given the inputs shown below. Initial state of signals X and Q are unknown (mark with xxx as needed) until the impact of the input signals propagate. X Q b) (4 pts) How would you size each transistor? Match the 2:1 inverter (including the clock). Draw the sizing next to the schematic. Calculate the switch model equivalent resistance(s) (note the equation given at the front of the exam for Req, switch model capacitance(s) (based on your sizing), and worst-case propagation delay through the circuit, max(tpLH,tpLH), where output is taken from Q and inputs are IN1 and IN2. c) (4 pts) Calculate the energy consumption from the VDD power supply of this circuit for the input pattern and time duration given in the timing diagram (previous page). Ignore the energy consumption related to driving IN1, IN2, and CLK. State any assumptions you need to make to determine a numerical value.

Assumptions for all problems (unless specified otherwise, give answers to 10% ): VDD(V) VT0( V) Body effect γ(V 0.5 ) VDSAT( V) k’ (A/V 2) λ(V -1 ) NMOS 2.0 0.4 0 0.5 500×10-6 0 PMOS -0.4 0 -0.5 -200×10-6 0 1. All transistors have the minimum length (Lunit = 250 nm) 2. Ignore body effect and channel length modulation 3. A transistor's intrinsic capacitance (cap) and gate cap are equal, i.e., Cint = Cg, γ = 1 4. The unit-sized transistor has Wunit = Lunit and intrinsic cap Cint = Cg = Cdb = Csb = 1.0fF. 5. For the unit sized inverter, β = (W/L)P / (W/L N = WP/WN = 2, WN = L = 250 nm 6. The unit sized transmission gate has a resistance Req,tr = 10kΩ and all caps of 1.0fF. a) (6 pts) How does the following circuit operate? In a few words/charts, describe what it does Sketch the waveforms of nodes X and Q given the inputs shown below. Initial state of signals X and Q are unknown (mark with xxx as needed) until the impact of the input signals propagate. X Q b) (4 pts) How would you size each transistor? Match the 2:1 inverter (including the clock). Draw the sizing next to the schematic. Calculate the switch model equivalent resistance(s) (note the equation given at the front of the exam for Req, switch model capacitance(s) (based on your sizing), and worst-case propagation delay through the circuit, max(tpLH,tpLH), where output is taken from Q and inputs are IN1 and IN2. c) (4 pts) Calculate the energy consumption from the VDD power supply of this circuit for the input pattern and time duration given in the timing diagram (previous page). Ignore the energy consumption related to driving IN1, IN2, and CLK. State any assumptions you need to make to determine a numerical value.
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