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(10 points) Determine the Pass Transistor Logic input assignments that realize the Boolean Coincidence function Y = A⊙B ≡ AB + AB¯.

(10 points) Determine the Pass Transistor Logic input assignments that realize the Boolean Coincidence function Y = A⊙B ≡ AB + AB¯.

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  1. (10 points) Determine the Pass Transistor Logic input assignments that realize the Boolean Coincidence function Y = A ⊙ B ≡ A B + A B ¯ .

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Design a CMOS logic gate for the function: Y = (A + B)(CD + E ). Assume that there is only a capacitance CL at the output node. There are no other capacitances at other nodes. a. Draw the circuit schematic for the logic gate. Show inputs clearly and number each transistors (e.g. MN1, MN2, ... for NMOS and MP1, MP2, .. for PMOS) b. Show the paths for worst and best case delays for both tPLH and tPHL. Determine delay times in terms of Req and CL. Give distinct Req values for each transistor (RMN1, RMN2, RMP1, RMP2, etc.). c. Assume there is an inverter designed in the same process as this logic gate that has the size of (W/L)P = k for PMOS and (W/L)N = m for NMOS. In order for the CMOS gate that realizes function Y to have the same tPLH and tPHL as this inverter at the worst case delay scenario, determine the size of each PMOS and NMOS in the gate you designed in terms of k and m respectively.
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a) Design a CMOS logic circuit to realize the following function Y = A¯B¯C + A¯BC¯ + AB¯C¯ by constructing both the Pull Up Network (PUN) and Pull Down Network (PDN). [6 points] b) Provide the W/L ratios for each transistor in the logic circuit obtained in a). Assume that for the basic inverter n = 2, p = 4 and L = 0.5 μm. [3 points ] c) Design a pass-transistor-logic circuit (transmission gate) to realize the function Y¯ = AB + A¯B¯. [3 points] d) Define the following parameters; and find them from the shown VTC [3 points ] i) VIH ii) VIL iii) NML iv) NMH

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