Question

Notify Me Bookmark

(10 Points) Transmission Gate and Logic Design a) Consider the circuit shown in Figure 4, write in the node voltages at the intermediate and output nodes. For the NMOS transistor use a threshold voltage of Vtn = 0.5 V. (Note: Show your steps for getting full credit) Figure 4 Transmission gate based circuit b) What is the logical equation for the circuit shown Figure 5. Write the truth table accordingly. Figure 5 Combinational Circuit

(10 Points) Transmission Gate and Logic Design a) Consider the circuit shown in Figure 4, write in the node voltages at the intermediate and output nodes. For the NMOS transistor use a threshold voltage of Vtn = 0.5 V. (Note: Show your steps for getting full credit) Figure 4 Transmission gate based circuit b) What is the logical equation for the circuit shown Figure 5. Write the truth table accordingly. Figure 5 Combinational Circuit

Image text
  1. (10 Points) Transmission Gate and Logic Design a) Consider the circuit shown in Figure 4, write in the node voltages at the intermediate and output nodes. For the NMOS transistor use a threshold voltage of Vtn = 0.5 V . (Note: Show your steps for getting full credit)
Figure 4 Transmission gate based circuit b) What is the logical equation for the circuit shown Figure 5. Write the truth table accordingly. Figure 5 Combinational Circuit

Detailed Answer

0 0

Please enter your email here. You will get email when this question is answered by our tutor.

Doubtrix Logo

Problem is not yet solved!

Click on Notify me to get email when question is answered.

Join Doubtrix with 7-days free trial

  • Icon Correct & Verified Answers
  • Icon No AI-Generated Answers
  • Icon Video Solution for Difficult Questions
  • Icon Work With Experts to Reach at Correct Answers
Notify me Login Sign Up

Similar/Related Questions

For the circuit shown in Figure 1, NMOS device M1 has the following properties: kn’(W/L) = 180 μA/V2, VT0 = 2 V, λ = 0.02 V-1, γ = 0.4 V1/2, 2ϕF = 0.7 V, and ID = 10 mA. Note that capacitor Cbig is a DC blocking cap, i.e., Cbig is an open at DC and a short at all other frequencies. Figure 1. Circuit for Problem 1. a) Determine the numerical value of bias voltage Vbias which is needed to achieve a drain current of ID = 10 mA. b) Draw the small-signal equivalent circuit. c) Analyze the small-signal circuit to find Rin, Rout, and Av = Vout/Vin. Find the analytic expression for each quantity first, before determining the numerical answers. d) Recall that gmb/gm = χ. Determine the numerical value of χ for this problem. [Note that this part has nothing to do with parts (b) and (c).] e) What is the threshold voltage of device M1? [Note that this part has nothing to do with parts (b) and (c).] Show your work, list all numerical values in proper engineering notation format with appropriate units and with at least two decimal places of precision.
Solution
0 0

Given the following circuit, assuming that all inputs of the circuit shown in Figure 1 below are initially 0 during the precharge phase and that all internal nodes are at 0V: a. Calculate the voltage drop on V0, if A changes to 1 (VDD = 2.5 V) during the evaluate phase. It is given that Vtn = 0.5 V, 2φF = 0.6 V and γ = 0.4 V0.5 . Hint: Don’t forget the body effect. b. Now calculate the voltage drop on Vo if both A and B change to 1 (under the above conditions). c. What is the maximum number of transistors that can be connected in series to M1 and M2 (including M1 and M2, excluding M0 ) if the output should not fall below 0.9 V during the evaluate phase? Assume that each one of the new transistors has the same intrinsic capacitance (to ground) as M1 and M2 (C=10fF).
Solution
1 0

Let us consider a NAND logic gate. This circuit implements the boolean function (A.B). The . stands for the AND operation, and the - stands for NOT; combining them, we get NAND! Figure 1: NAND gate transistor-level implementation. Vtn and Vtp are the threshold voltages for the NMOS and PMOS transistors, respectively. Assume that VDD > Vtn, |Vtp| > 0. (a) Label the gate, source, and drain nodes for the NMOS and PMOS transistors (please redraw the circuit). (b) If VA = VDD and VB = VDD, which transistors act like open switches? Which transistors act like closed switches? What is Vout? (c) If VA = 0V and VB = VDD, what is Vout? (d) If VA = VDD and VB = 0V, what is Vout? (e) If VA = 0V and VB = 0V, what is Vout? (f) Write out the truth table for this circuit.

Let us consider a NAND logic gate. This circuit implements the boolean function (A.B). The . stands for the AND operation, and the - stands for NOT; combining them, we get NAND! Figure 1: NAND gate transistor-level implementation. Vtn and Vtp are the threshold voltages for the NMOS and PMOS transistors, respectively. Assume that VDD > Vtn, |Vtp| > 0. (a) Label the gate, source, and drain nodes for the NMOS and PMOS transistors (please redraw the circuit). (b) If VA = VDD and VB = VDD, which transistors act like open switches? Which transistors act like closed switches? What is Vout? (c) If VA = 0V and VB = VDD, what is Vout? (d) If VA = VDD and VB = 0V, what is Vout? (e) If VA = 0V and VB = 0V, what is Vout? (f) Write out the truth table for this circuit.
Solution
1 0