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16.17 The voltage-transfer characteristic of a particular logic inverter is modeled by three straight-line segments in the manner shown in Fig. 16.13. If VIL = 1.1 V, VIH = 1.2 V, VOL = 0.3 V, and VOH = 1.5 V, find: (a) the noise margins (b) the value of VM (c) the voltage gain in the transition region Figure 16.13 Voltage-transfer characteristic of an inverter. The VTC is approximated by three straight-line segments. Note the four parameters of the VTC (VOH, VOL, VIL, and VIH) and their use in determining the noise margins (NMH and NML).

16.17 The voltage-transfer characteristic of a particular logic inverter is modeled by three straight-line segments in the manner shown in Fig. 16.13. If VIL = 1.1 V, VIH = 1.2 V, VOL = 0.3 V, and VOH = 1.5 V, find: (a) the noise margins (b) the value of VM (c) the voltage gain in the transition region Figure 16.13 Voltage-transfer characteristic of an inverter. The VTC is approximated by three straight-line segments. Note the four parameters of the VTC (VOH, VOL, VIL, and VIH) and their use in determining the noise margins (NMH and NML).

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16.17 The voltage-transfer characteristic of a particular logic inverter is modeled by three straight-line segments in the manner shown in Fig. 16.13. If V I L = 1.1 V , V I H = 1.2 V , V O L = 0.3 V , and V O H = 1.5 V , find: (a) the noise margins (b) the value of V M (c) the voltage gain in the transition region
Figure 16.13 Voltage-transfer characteristic of an inverter. The VTC is approximated by three straight-line segments. Note the four parameters of the VTC ( V O H , V O L , V I L , and V I H ) and their use in determining the noise margins ( N M H and N M L ) .

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(a) State the advantages of the CMOS inverter over the NMOS inverter. (b) Realize the following logic function using NMOS & CMOs logic gates. F = (A+B).(C+D).E (c) For a particular logic family for which the supply voltage is V+, VOL = 0.18 V+. VOH = 0.87 V+, VIL = 0.35 V+, and VIH = 0.55 V+. (i) What are the noise margins (NML and NMH)? (ii) What is the width of transition region? (iii) For a maximum noise margin of 2 V, what value of V + is required (d) If VA = 4 V, find Vout for the NMOS inverter shown in figure 5. (Given VT = 1 V and μnCox = 40 μA/V2) (e) If VA = VB = VC = 4 V, find Vout for the 3 input NAND gate shown in Figure 6. (Given VT = 1 V and μnCox = 40 μA/V2)
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1.1 The voltage transfer characteristic (VTC) for a logic inverter is shown in Figure P1.1. For this inverter, determine the following: (a) VOH, VOL, VIL, VIH and VM (b) the logic swing (c) the transition width (d) the noise margins, noise sensitivities, and noise immunity levels

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