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(25 pt) Prob 2. Implement the logic function Y = (AB+C).D¯ in 18 -nm FinFET CMOS technology. a) Size the transistors so that the output resistance is the same as that of an inverter with nfinn = 2 for the nMOS and nfinp = 3 for the pMOS b) What input combination(s) result in the worst case tpHL and tpLH ?

(25 pt) Prob 2. Implement the logic function Y = (AB+C).D¯ in 18 -nm FinFET CMOS technology. a) Size the transistors so that the output resistance is the same as that of an inverter with nfinn = 2 for the nMOS and nfinp = 3 for the pMOS b) What input combination(s) result in the worst case tpHL and tpLH ?

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( 25 p t ) Prob 2. Implement the logic function Y = ( A B + C ) . D ¯ in 18 -nm FinFET CMOS technology. a) Size the transistors so that the output resistance is the same as that of an inverter with n f i n n = 2 for the n M O S and n f i n p = 3 for the p M O S b) What input combination(s) result in the worst case t p H L and t p L H ?

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