Question

Notify Me Bookmark

3(a) A CMOS circuit is shown in Figure 4. Size the transistors in the circuit for more or less symmetrical delay under worst case conditions. Minimize the size as much as possible. Assume un = 2up. Show the size of each transistor in the diagram. Use a minimum transistor size of 10/2. (Note: Certain paths wont happen.) b) Redesign the circuit to minimize the number of transistors (you may use either pass logic or gate logic design).

3(a) A CMOS circuit is shown in Figure 4. Size the transistors in the circuit for more or less symmetrical delay under worst case conditions. Minimize the size as much as possible. Assume un = 2up. Show the size of each transistor in the diagram. Use a minimum transistor size of 10/2. (Note: Certain paths wont happen.) b) Redesign the circuit to minimize the number of transistors (you may use either pass logic or gate logic design).

Image text
3(a) A CMOS circuit is shown in Figure 4. Size the transistors in the circuit for more or less symmetrical delay under worst case conditions. Minimize the size as much as possible. Assume un = 2up. Show the size of each transistor in the diagram. Use a minimum transistor size of 10/2. (Note: Certain paths wont happen.) b) Redesign the circuit to minimize the number of transistors (you may use either pass logic or gate logic design).

Detailed Answer

0 0

Please enter your email here. You will get email when this question is answered by our tutor.

Doubtrix Logo

Problem is not yet solved!

Click on Notify me to get email when question is answered.

Join Doubtrix with 7-days free trial

  • Icon Correct & Verified Answers
  • Icon No AI-Generated Answers
  • Icon Video Solution for Difficult Questions
  • Icon Work With Experts to Reach at Correct Answers
Login Sign Up

Similar/Related Questions

Design a CMOS logic gate for the function: Y = (A + B)(CD + E ). Assume that there is only a capacitance CL at the output node. There are no other capacitances at other nodes. a. Draw the circuit schematic for the logic gate. Show inputs clearly and number each transistors (e.g. MN1, MN2, ... for NMOS and MP1, MP2, .. for PMOS) b. Show the paths for worst and best case delays for both tPLH and tPHL. Determine delay times in terms of Req and CL. Give distinct Req values for each transistor (RMN1, RMN2, RMP1, RMP2, etc.). c. Assume there is an inverter designed in the same process as this logic gate that has the size of (W/L)P = k for PMOS and (W/L)N = m for NMOS. In order for the CMOS gate that realizes function Y to have the same tPLH and tPHL as this inverter at the worst case delay scenario, determine the size of each PMOS and NMOS in the gate you designed in terms of k and m respectively.
Solution
0 0

Problem 1: Consider the logic circuit below to the left: (a) What is the logic function implemented by the design below? (b) Size NMOS and PMOS devices in the circuit below so that the worst-case pull-up and pull-down strength of the circuit is exactly as much as in the inverter shown to the right. Assume that all the transistors in the circuit above and in the inverter have a minimum channel length (LMIN). In the inverter, the width of NMOS is WMIN and PMOS is 2×WMN. (c) For the logic design, identify the transition for the worst case 'high to low' and 'low to high' delay considering that only one of the input (among A, B, C) switches. Compute RC delay for these transitions. Assume that the resistance of a minimum width width (WMIN), the junction capacitance is C at each source and drain ends. Ignore any external load capacitance for the circuit.

Solution
0 0

Vtn = 0.8 V, Vtp = -0.9 V, a) Find the logic expression for Z. What function does this circuit implement? b) Draw the pull-up network that completes the CMOS logic circuit. c) Assume that the equivalent inverter has an NMOS transistor with a minimum size of 2 um/250 nm. Determine the equivalent PMOS transistor dimensions (W/L) that ensure tPHL = tPLH for the equivalent inverter. d) Find the NMOS and PMOS transistor dimensions in the CMOS logic circuit so that the propagation delays are equal to the value you found for the inverter in c) for the worst case, assuming an equal load capacitance for both the inverter and the logic circuit. Vtn = 0.8 V, Vtp = -0.9 V, unCox = 250 uA/V2, upCox = 120 uA/V2 is given. The pull-down section of a CMOS logic circuit is shown below. = 250 a) Find the logic expression for Z. What function does this circuit implement? b) Draw the pull-up network that completes the CMOS logic circuit. c) Assume that the equivalent inverter has an NMOS transistor with a minimum size of 2 um/250 nm. Determine the equivalent PMOS transistor dimensions (W/L) that ensure tPHL = tPLH for the equivalent inverter. d) Find the NMOS and PMOS transistor dimensions in the CMOS logic circuit so that the propagation delays are equal to the value you found for the inverter in c) for the worst case, assuming an equal load capacitance for both the inverter and the logic circuit. Vtn = 0.8 V, Vtp = -0.9 V, unCox = 250 uA/V2, upCox = 120 uA/V2 is given. The pull-down section of a CMOS logic circuit is shown below., a) Find the logic expression for Z. What function does this circuit implement? b) Draw the pull-up network that completes the CMOS logic circuit. c) Assume that the equivalent inverter has an NMOS transistor with a minimum size of 2 um/250 nm. Determine the equivalent PMOS transistor dimensions (W/L) that ensure tPHL = tPLH for the equivalent inverter. d) Find the NMOS and PMOS transistor dimensions in the CMOS logic circuit so that the propagation delays are equal to the value you found for the inverter in c) for the worst case, assuming an equal load capacitance for both the inverter and the logic circuit. Vtn = 0.8 V, Vtp = -0.9 V, unCox = 250 uA/V2, upCox = 120 uA/V2 is given. The pull-down section of a CMOS logic circuit is shown below. =120 a) Find the logic expression for Z. What function does this circuit implement? b) Draw the pull-up network that completes the CMOS logic circuit. c) Assume that the equivalent inverter has an NMOS transistor with a minimum size of 2 um/250 nm. Determine the equivalent PMOS transistor dimensions (W/L) that ensure tPHL = tPLH for the equivalent inverter. d) Find the NMOS and PMOS transistor dimensions in the CMOS logic circuit so that the propagation delays are equal to the value you found for the inverter in c) for the worst case, assuming an equal load capacitance for both the inverter and the logic circuit. Vtn = 0.8 V, Vtp = -0.9 V, unCox = 250 uA/V2, upCox = 120 uA/V2 is given. The pull-down section of a CMOS logic circuit is shown below. is given. The pull-down section of a CMOS logic circuit is shown below.

a) Find the logic expression for Z. What function does this circuit implement?

b) Draw the pull-up network that completes the CMOS logic circuit.

c) Assume that the equivalent inverter has an NMOS transistor with a minimum size of 2 müm/250 nm. Determine the equivalent PMOS transistor dimensions (W/L) that ensure a) Find the logic expression for Z. What function does this circuit implement? b) Draw the pull-up network that completes the CMOS logic circuit. c) Assume that the equivalent inverter has an NMOS transistor with a minimum size of 2 um/250 nm. Determine the equivalent PMOS transistor dimensions (W/L) that ensure tPHL = tPLH for the equivalent inverter. d) Find the NMOS and PMOS transistor dimensions in the CMOS logic circuit so that the propagation delays are equal to the value you found for the inverter in c) for the worst case, assuming an equal load capacitance for both the inverter and the logic circuit. Vtn = 0.8 V, Vtp = -0.9 V, unCox = 250 uA/V2, upCox = 120 uA/V2 is given. The pull-down section of a CMOS logic circuit is shown below. for the equivalent inverter.

d) Find the NMOS and PMOS transistor dimensions in the CMOS logic circuit so that the propagation delays are equal to the value you found for the inverter in c) for the worst case, assuming an equal load capacitance for both the inverter and the logic circuit.

a) Find the logic expression for Z. What function does this circuit implement? b) Draw the pull-up network that completes the CMOS logic circuit. c) Assume that the equivalent inverter has an NMOS transistor with a minimum size of 2 um/250 nm. Determine the equivalent PMOS transistor dimensions (W/L) that ensure tPHL = tPLH for the equivalent inverter. d) Find the NMOS and PMOS transistor dimensions in the CMOS logic circuit so that the propagation delays are equal to the value you found for the inverter in c) for the worst case, assuming an equal load capacitance for both the inverter and the logic circuit. Vtn = 0.8 V, Vtp = -0.9 V, unCox = 250 uA/V2, upCox = 120 uA/V2 is given. The pull-down section of a CMOS logic circuit is shown below.
Solution
0 0