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5.55. What is the on-resistance and voltage VO for the parallel combination of the NMOS (W/L = 14/1) and PMOS (W/L = 35/1) transistors in Fig. P5.55 for VIN = 0 V? (b) For VIN = 5 V? This circuit is called a transmission-gate. Figure P5.55

5.55. What is the on-resistance and voltage VO for the parallel combination of the NMOS (W/L = 14/1) and PMOS (W/L = 35/1) transistors in Fig. P5.55 for VIN = 0 V? (b) For VIN = 5 V? This circuit is called a transmission-gate. Figure P5.55

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5.55. What is the on-resistance and voltage V O for the parallel combination of the NMOS ( W L = 14 / 1 ) and PMOS ⁡ ( W / L = 35 / 1 ) transistors in Fig. P5.55 for V I N = 0 V ? (b) For V I N = 5 V ? This circuit is called a transmission-gate.
Figure P5.55

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What is the on-resistance and voltage VO for the parallel combination of the NMOS (W/L = 14/1) and PMOS (W/L = 35/1) transistors in Fig. P5.55 for VIN = 0 V? (b) For VIN = 5 V? This circuit is called a transmission-gate. Figure P5.55

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Consider the NMOS inverter with depletion load in Figure 16.7(a). Let VDD = 1.8 V, and assume VTND = 0.3 V and VTNL = -0.6 V. (a) Design the circuit such that the power dissipation is 80μW and the output voltage is vO = 0.06 V when vI is a logic 1. (b) Using the results of part (a), determine the transition points for the driver and load transistors. (c) If (W/L)D found in part (a) is doubled, what is the maximum power dissipation in the inverter and what is vO when vI is a logic 1? The NMOS inverter with depletion load is shown in Figure 16.7(a). The bias is VDD = 2.5 V. The transistor parameters are VTND = 0.5 V and VTNL = -1 V. The width-to-length ratio of the load device is W/L = 1. (a) Design the driver transistor such that vO = 0.05 V when the input is a logic 1. (b) What is the power dissipated in the circuit when vI = 2.5 V?

Consider the NMOS inverter with depletion load in Figure 16.7(a). Let VDD = 1.8 V, and assume VTND = 0.3 V and VTNL = -0.6 V. (a) Design the circuit such that the power dissipation is 80μW and the output voltage is vO = 0.06 V when vI is a logic 1. (b) Using the results of part (a), determine the transition points for the driver and load transistors. (c) If (W/L)D found in part (a) is doubled, what is the maximum power dissipation in the inverter and what is vO when vI is a logic 1? The NMOS inverter with depletion load is shown in Figure 16.7(a). The bias is VDD = 2.5 V. The transistor parameters are VTND = 0.5 V and VTNL = -1 V. The width-to-length ratio of the load device is W/L = 1. (a) Design the driver transistor such that vO = 0.05 V when the input is a logic 1. (b) What is the power dissipated in the circuit when vI = 2.5 V?
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[MOSFET Circuits] Consider the MOSFET circuit as shown below. R = 1kΩ, kn’ = 1 mA/V2 and Vtn = 0.3 V for both Q1 and Q2, W/L = 0.5μm/0.1μm for Q1, W/L = 1μm/0.1μm for Q2, λ = 0 and vSB = 0. (a) Calculate the voltage at the drain terminal of Q1. (b) What is the ratio of iD1 to iD2, where iD1 is the drain current for Q1 and iD2 is the drain current for Q2. Hint: This circuit is called the "current mirror" circuit, where the ratio of iD1 to iD2 is a fixed number, determined by W1, W2, L1 and L2, as long as both transistors are biased in saturation mode. (c) What is the maximum value of R2 so that Q2 remains in saturation mode?
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