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7.5 For the gate shown in Fig. P7.5, Pull-up transistor ratio is 5/5 Pull-down transistor ratios are 100/5 VTn = 0.53 V VTp = −0.51 V γ = 0.574 V1 /2 |2ΦF| = 1.020 V EC,pLp = 1.8 V a. Identify the worst-case input combination(s) for VOL. b. Calculate the worst-case value of VOL. (Assume that all pull-down transistors have the same body bias and initially, that VOL ≈ 5% VDD. ) Figure P7.5

7.5 For the gate shown in Fig. P7.5, Pull-up transistor ratio is 5/5 Pull-down transistor ratios are 100/5 VTn = 0.53 V VTp = −0.51 V γ = 0.574 V1 /2 |2ΦF| = 1.020 V EC,pLp = 1.8 V a. Identify the worst-case input combination(s) for VOL. b. Calculate the worst-case value of VOL. (Assume that all pull-down transistors have the same body bias and initially, that VOL ≈ 5% VDD. ) Figure P7.5

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7.5 For the gate shown in Fig. P7.5,
  • Pull-up transistor ratio is 5 / 5
  • Pull-down transistor ratios are 100/5
  • V T n = 0.53 V
  • V T p = − 0.51 V ■ γ = 0.574 V 1 / 2
  • | 2 Φ F | = 1.020 V
  • E C , p L p = 1.8 V a. Identify the worst-case input combination(s) for V O L . b. Calculate the worst-case value of V O L . (Assume that all pull-down transistors have the same body bias and initially, that V O L ≈ 5 % V D D .) Figure P7.5

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