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A CS amplifier using an NMOS transistor biased in the manner of the circuit below, for which gm = 2 mA/V is found to have an overall voltage gain Gv of -20 V/V. What value should a resistance Rs inserted in the source lead have to reduce the voltage gain by a factor of 4?

A CS amplifier using an NMOS transistor biased in the manner of the circuit below, for which gm = 2 mA/V is found to have an overall voltage gain Gv of -20 V/V. What value should a resistance Rs inserted in the source lead have to reduce the voltage gain by a factor of 4?

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A CS amplifier using an NMOS transistor biased in the manner of the circuit below, for which gm = 2 mA/V is found to have an overall voltage gain Gv of -20 V/V. What value should a resistance Rs inserted in the source lead have to reduce the voltage gain by a factor of 4?

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