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A current mirror is shown in the figure below. The circuit is designed to mirror an input current of Iin = 0.5 mA. In the circuit, RS = 250 Ω. The two transistors are identical, with the parameters of μnCox = 270 μA/V2, λL = 0.08 μm/V, W/L = 20 μm/0.2 μm, and Vt = 0.5 V. Find: (1) The output current Iout of the circuit (ignore the channel length modulation effect). (2) The minimum output voltage of the current mirror (ignore the channel length modulation effect). (3) The output resistance Rout of the circuit (include the channel length modulation effect). Hint: for part (3), apply the general method of finding the output resistance of a circuit first.

A current mirror is shown in the figure below. The circuit is designed to mirror an input current of Iin = 0.5 mA. In the circuit, RS = 250 Ω. The two transistors are identical, with the parameters of μnCox = 270 μA/V2, λL = 0.08 μm/V, W/L = 20 μm/0.2 μm, and Vt = 0.5 V. Find: (1) The output current Iout of the circuit (ignore the channel length modulation effect). (2) The minimum output voltage of the current mirror (ignore the channel length modulation effect). (3) The output resistance Rout of the circuit (include the channel length modulation effect). Hint: for part (3), apply the general method of finding the output resistance of a circuit first.

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A current mirror is shown in the figure below. The circuit is designed to mirror an input current of Iin = 0.5 mA. In the circuit, RS = 250 Ω. The two transistors are identical, with the parameters of μnCox = 270 μA/V2, λL = 0.08 μm/V, W/L = 20 μm/0.2 μm, and Vt = 0.5 V. Find: (1) The output current Iout of the circuit (ignore the channel length modulation effect). (2) The minimum output voltage of the current mirror (ignore the channel length modulation effect). (3) The output resistance Rout of the circuit (include the channel length modulation effect). Hint: for part (3), apply the general method of finding the output resistance of a circuit first.

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A differential amplifier circuit is shown in the figure below. In the circuit, VDD = +10 V, the current I provided by the current source is 2 mA and the internal source resistance is RSS = 50 kΩ. The transistor parameters are as follows: - All NMOS: μnCox = 100 μA/ V2, W/L = 10 μm/1.6 μm, Vtn = 0.7V, λnL = 0.10 μm/V - All PMOS: μpCox = 50 μA/V2, W/L = 10μm/1.6μm, Vtp = −0.8 V, λpL = 0.05 μm/V (1) Calculate the DC output voltage VO (ignore the channel length modulation effect of all transistors). (2) Under the differential mode operation (i.e., v1 = 1/2vd, v2 = -1/2vd ), calculate the differential mode small signal voltage gain Ad = vo/vd (include the channel length modulation effect of all transistors). Hint: please pay special attention to the connections of Q3 and Q4 transistors.
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Current Mirrors (35 points) This problem introduces current mirrors, which will be covered in more details in future lectures. Consider the circuit shown below (Figure 2). (W/L)1 = 1, (W/L)2 = 5, Rref = 50 kΩ, ignore channel length modulation unless otherwise stated. Assume L1 = L2 = 1 μm. Figure 2 a) (5 points) Assume RL = 10 kΩ. Calculate IL, the current flowing through RL. What is the current mirroring ratio ( IL over Iref , where Iref is the current through Rref )? We want the current mirror to provide a load-independent current as much as possible, so check that M2 is in saturation. b) (5 points) Determine the maximum RL and minimum VOut such that the current mirror still functions with the same current mirroring ratio you calculated in part a). Hint: for the current mirror to function as desired, transistor saturation should be maintained. c) (5 points) Channel length modulation introduces load-dependent errors in the mirroring ratio. Using λ = 0.1 V−1 for L = 1 μm, estimate the percentage error in the mirroring ratio. Here, set RL to its maximum value you got in part b ), and assume that we want the same IL as in parts a) and b). Hint: what should be the new VX and Iref ? d) (4 points) Compute the output resistance, Rout, , looking into the drain of M2. Use λ = 0.1 V−1 and assume the same IL as in parts a) through c). e) (5 points) Now consider redesigning the previous current mirror with source-degenerated transistors as shown in Figure 3. Ignore channel length modulation and body effect ( Assume bulk is tied to source). Transistor sizes remain the same, (WL)1 = 1 and (WL)2 = 5. This circuit has been designed to have the same Iref as in part a). What should the value of Rs2 be if we want the same current mirroring ratio as in a)? f) (5 points) Similarly to part b, determine the maximum RL and minimum VOut such that the current mirror still functions with the same current mirroring ratio as in part e). g) (4 points) Now compute the output resistance, Rout , looking into the drain of M2 (using λ = 0.1 V−1 ). Assume IL as used in parts e) and f ). h) (2 points) Comparing the minimum output voltage and the output resistance of these two current mirrors, comment on the advantages and disadvantages of using source degeneration in a current mirror. Figure 3 Current Mirrors (35 points) This problem introduces current mirrors, which will be covered in more details in future lectures. Consider the circuit shown below (Figure 2). (W/L)1 = 1, (W/L)2 = 5, Rref = 50 kΩ, ignore channel length modulation unless otherwise stated. Assume L1 = L2 = 1 μm. Figure 2 a) (5 points) Assume RL = 10 kΩ. Calculate IL, the current flowing through RL. What is the current mirroring ratio ( IL over Iref , where Iref is the current through Rref )? We want the current mirror to provide a load-independent current as much as possible, so check that M2 is in saturation. b) (5 points) Determine the maximum RL and minimum VOut such that the current mirror still functions with the same current mirroring ratio you calculated in part a). Hint: for the current mirror to function as desired, transistor saturation should be maintained. c) (5 points) Channel length modulation introduces load-dependent errors in the mirroring ratio. Using λ = 0.1 V−1 for L = 1 μm, estimate the percentage error in the mirroring ratio. Here, set RL to its maximum value you got in part b ), and assume that we want the same IL as in parts a) and b). Hint: what should be the new VX and Iref ? d) (4 points) Compute the output resistance, Rout, , looking into the drain of M2. Use λ = 0.1 V−1 and assume the same IL as in parts a) through c). e) (5 points) Now consider redesigning the previous current mirror with source-degenerated transistors as shown in Figure 3. Ignore channel length modulation and body effect ( Assume bulk is tied to source). Transistor sizes remain the same, (WL)1 = 1 and (WL)2 = 5. This circuit has been designed to have the same Iref as in part a). What should the value of Rs2 be if we want the same current mirroring ratio as in a)? f) (5 points) Similarly to part b, determine the maximum RL and minimum VOut such that the current mirror still functions with the same current mirroring ratio as in part e). g) (4 points) Now compute the output resistance, Rout , looking into the drain of M2 (using λ = 0.1 V−1 ). Assume IL as used in parts e) and f ). h) (2 points) Comparing the minimum output voltage and the output resistance of these two current mirrors, comment on the advantages and disadvantages of using source degeneration in a current mirror. Figure 3

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For all circuits, do not consider channel length modulation for calculating bias points. Unless otherwise specified, channel length modulation effect needs to be considered for small-signal analysis. All answers should be given to the second decimal place. Circuit and device parameters are: Vdd = 5 V;VTn = VTp = 1 V; μnCox = 50 μA/V2; μpCox = 25 μA/V2; λn = λp = 0.01 V−1; Lmin = 1 μm Figure 1 (for problems 1-3) Figure 2 (for problems 5-9) Figure 1: Transistor M1 has (W/L) = (160 μm/2 μm) and a bias current Iout = 2 mA. We desire M1 to be in saturation. You should assume λn = 0 for problems (1)-(3). Determine the ratio R1 /R2 required. 1 point Let VTn increase by 10% to 1.1 V. What is the new value of Iout in mA ? 1 point Let μnCox increase by 10% to 55 μA/V2. What is the new value of Iout in mA ? 1 point Figure 2: The circuit has Iref = 2 mA and Vp = 4 V. Transistors M1, M2 and M3 have (W/L) = (80 μm/1 μm). Determine the value of vx. (in volts) 1 point Determine the minimum allowable value of Vb (in volts) such that all devices are in saturation. 1 point Determine the maximum allowable value of Vb (in volts) such that all devices are in saturation. 1 point Determine Vb (in volts) such that vX = VY. 1 point determine the output resistance of this circuit ∂Vp/∂Iout in MΩ. 1 point Description for questions 9-10: An NMOS device with ID = 1 mA must operate in saturation with drain-source voltages as low as 0.5 V. The minimum required small-signal output impedance is 400 kQ. {Hint: You need to use the relations: rout = 1 /(λ⋅ID); λ⋅L = constant; and expression for VDS, sat = VGS−VT} Determine the length of the device in μm. 1 point Determine the width of the device in μm. 1 point

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