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(A) Design a CMOS inverter in LTSpice environment with VDD = 1.8 V. (B) Consider the pull-down network (PDN) given as follows:Calculate the logic function of the given circuit topology. Implement the pull-up network (PUN) of the function. Size the transistors so the gate will operate similar to an optimized inverter with β = 2.

(A) Design a CMOS inverter in LTSpice environment with VDD = 1.8 V. (B) Consider the pull-down network (PDN) given as follows:Calculate the logic function of the given circuit topology. Implement the pull-up network (PUN) of the function. Size the transistors so the gate will operate similar to an optimized inverter with β = 2.

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(A) Design a CMOS inverter in LTSpice environment with VDD = 1.8 V . (B) Consider the pull-down network (PDN) given as follows:
  1. Calculate the logic function of the given circuit topology.
  2. Implement the pull-up network (PUN) of the function.
  3. Size the transistors so the gate will operate similar to an optimized inverter with β = 2 .

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